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公开(公告)号：US10003347B2
公开(公告)日：2018-06-19
申请号：US15711177
申请日：2017-09-21
Applicant: Maxlinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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22.发明申请公开(公告)号：US20180069562A1
公开(公告)日：2018-03-08
申请号：US15812365
申请日：2017-11-14
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
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公开(公告)号：US20180048301A1
公开(公告)日：2018-02-15
申请号：US15793581
申请日：2017-10-25
Applicant: Maxlinear, Inc.
Inventor： Yongjian Tang , Xuefeng Chen
IPC: H03K17/06
CPC classification number: H03K17/063 , H03K17/687 , H03K2217/0054
Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.
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公开(公告)号：US09837958B2
公开(公告)日：2017-12-05
申请号：US15177045
申请日：2016-06-08
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Hosein Zareie
CPC classification number: H03B1/04 , H03B5/32 , H03B5/362 , H03B5/364 , H03B2202/044 , H03B2202/05
Abstract: Systems and methods are provided for a crystal (xtal) oscillator with high interference immunity. Generated reference signals may be processed to mitigate effects of interference. The processing may comprise filtering, particularly at harmonic positions, to remove or greatly reduce interference signals.
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公开(公告)号：US20170170818A1
公开(公告)日：2017-06-15
申请号：US15444662
申请日：2017-02-28
Applicant: Maxlinear, Inc.
Inventor： Yongjian Tang , Xuefeng Chen
IPC: H03K17/06
CPC classification number: H03K17/063 , H03K17/687 , H03K2217/0054
Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.
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Patent Agency Ranking
公开(公告)号：US20170134032A1
公开(公告)日：2017-05-11
申请号：US15230735
申请日：2016-08-08
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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27.发明授权Method and system for asynchronous successive approximation analog-to-digital convertor (ADC) architecture 有权异步逐次逼近模数转换器（ADC）架构的方法和系统公开(公告)号：US09537503B2
公开(公告)日：2017-01-03
申请号：US15151042
申请日：2016-05-10
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Kok Lim Chan , Eric Fogleman , Sheng Ye
CPC classification number: H03M1/38 , H03M1/06 , H03M1/0682 , H03M1/125 , H03M1/466
Abstract: Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions.
Abstract translation: 提供了用于在信号处理期间检测元稳定性的系统和方法。 元稳定性检测器可以包括定时控制电路，多个信号调整电路和多个信号状态电路。 定时控制电路可以测量模数转换期间每个转换周期的比较时间。 每个信号调整电路可以向信号调整电路的一个或多个输入信号施加逻辑运算，并提供对应的输出信号。 至少一个处理周期，每个信号状态电路可以将与一个或多个输入信号有关的状态信息存储到信号状态电路; 并基于先前存储的信息提供输出信号。 多个信号状态电路，多个信号调节电路和定时控制电路可以被布置成在模数转换期间产生用于控制模数转换器（ADC）的一个或多个控制信号。
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公开(公告)号：US20160359455A1
公开(公告)日：2016-12-08
申请号：US15177045
申请日：2016-06-08
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Hosein Zareie
CPC classification number: H03B1/04 , H03B5/32 , H03B5/362 , H03B5/364 , H03B2202/044 , H03B2202/05
Abstract: Systems and methods are provided for a crystal (xtal) oscillator with high interference immunity. Generated reference signals may be processed to mitigate effects of interference. The processing may comprise filtering, particularly at harmonic positions, to remove or greatly reduce interference signals.
Abstract translation: 提供了具有高抗干扰能力的晶体（xtal）振荡器的系统和方法。 可以处理生成的参考信号以减轻干扰的影响。 该处理可以包括滤波，特别是在谐波位置处，以去除或大大降低干扰信号。
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29.发明授权Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCS) 有权异步逐次逼近寄存器（SAR）模数转换器（ADCS）的方法和系统公开(公告)号：US09413378B2
公开(公告)日：2016-08-09
申请号：US14843445
申请日：2015-09-02
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits.
Abstract translation: 提供了利用抢占位设置决定的异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统。 特别地，这样的SAR ADC可以可操作用于当发生针对每个比较步骤确定有效输出判定的故障时，设置一个或多个剩余的位，直到但不包括一个或多个重叠的冗余位在对应于 比较步骤，到一个特定的价值。 该值可以从紧接在前的判定中确定的比特的值导出。 可以基于动态和/或适应性标准来确定故障。 可以设置标准，例如，以便确保SAR模拟输入电压与其中使用的数模转换器（DAC）的模拟输出电压之间的差异幅度在电压的重叠范围内 对应于重叠的冗余位。
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公开(公告)号：US20150188536A1
公开(公告)日：2015-07-02
申请号：US14585707
申请日：2014-12-30
Applicant: Maxlinear, Inc.
Inventor： Yongjian Tang , Xuefeng Chen
IPC: H03K17/687 , H03K17/06
CPC classification number: H03K17/063 , H03K17/687 , H03K2217/0054
Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor. The pull-down path includes a diode-connected MOS transistor coupled in parallel with a second MOS transistor that couples the gate terminal of the switching MOS transistor to ground via third and fourth MOS transistors when the switching MOS transistor is in an OFF state. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage, VDD, to activate the pull-down path. A capacitor may be coupled between gate and source terminals of the switching MOS transistor to switch the switching MOS transistor to an ON state.
Abstract translation: 用于可靠自举开关的方法和系统可以包括用自举开关对接收到的信号进行采样，其中自举开关包括具有耦合到开关MOS晶体管的栅极端子的下拉通路的开关金属氧化物半导体（MOS）晶体管。 下拉路径包括与第二MOS晶体管并联耦合的二极管连接的MOS晶体管，当开关MOS晶体管处于截止状态时，第二MOS晶体管通过第三和第四MOS晶体管将开关MOS晶体管的栅极端子接地。 第三和第四MOS晶体管可以与第二MOS晶体管串联。 第四晶体管的栅极端子可以从地切换到电源电压VDD，以激活下拉路径。 电容器可以耦合在开关MOS晶体管的栅极和源极端子之间，以将开关MOS晶体管切换到导通状态。
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