公开(公告)号：US08737126B2

公开(公告)日：2014-05-27

申请号：US13653424

申请日：2012-10-17

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Kuo-Yi Cheng ,  Chun-Yen Chang

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C7/00

CPC classification number: G11C16/10 ,  G11C7/00 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3468 ,  G11C16/3495 ,  G11C2211/5621

Abstract: A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and adjusting an initial write voltage and a write voltage pulse time corresponding to the memory cell based on the wear degree thereof. The method further includes programming the memory cell by applying the initial write voltage and the write voltage pulse time, thereby writing the data into the memory cell. Accordingly, data can be accurately stored into the rewritable non-volatile memory module by the method.

Abstract translation: 一种用于将数据写入可重写非易失性存储器模块的存储单元的数据写入方法，以及使用相同区域的存储器控​​制器和存储器存储装置。 该方法包括记录存储单元的磨损程度，并且基于其磨损程度调整对应于存储单元的初始写入电压和写入电压脉冲时间。 该方法还包括通过施加初始写入电压和写入电压脉冲时间对存储器单元进行编程，从而将数据写入存储单元。 因此，可以通过该方法将数据精确地存储到可重写非易失性存储器模块中。

公开(公告)号：US12293784B2

公开(公告)日：2025-05-06

申请号：US18301275

申请日：2023-04-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Hao Chen ,  Po-Cheng Su ,  Shih-Jia Zeng ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G11C7/00 ,  G06F3/06 ,  G11C11/409 ,  G11C16/26

Abstract: A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.

公开(公告)号：US20240128987A1

公开(公告)日：2024-04-18

申请号：US17994399

申请日：2022-11-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Yi-Fang Chang ,  Chun-Wei Tsao ,  Chen-An Hsu ,  Wei Lin

IPC: H03M13/15 ,  H03M13/01

CPC classification number: H03M13/1555 ,  H03M13/015 ,  H03M13/1575

Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.

公开(公告)号：US11573704B2

公开(公告)日：2023-02-07

申请号：US16529807

申请日：2019-08-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Hsiao-Yi Lin ,  Yu-Siang Yang

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/04

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.

公开(公告)号：US20220027089A1

公开(公告)日：2022-01-27

申请号：US16994668

申请日：2020-08-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Yu-Siang Yang ,  Szu-Wei Chen ,  Wei Lin

IPC: G06F3/06 ,  G11C16/26

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.

公开(公告)号：US10978163B2

公开(公告)日：2021-04-13

申请号：US16601517

申请日：2019-10-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G11C16/26 ,  G11C11/56 ,  H03M7/42

Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.

公开(公告)号：US10936248B2

公开(公告)日：2021-03-02

申请号：US16452540

申请日：2019-06-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu

IPC: G06F3/06 ,  G06F12/02

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.

公开(公告)号：US20200168289A1

公开(公告)日：2020-05-28

申请号：US16251105

申请日：2019-01-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Yu-Cheng Hsu ,  Yu-Siang Yang

IPC: G11C29/50 ,  G06F3/06 ,  G11C29/12 ,  G11C29/14

Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.

公开(公告)号：US20200034232A1

公开(公告)日：2020-01-30

申请号：US16120314

申请日：2018-09-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Yu-Siang Yang ,  Yu-Cheng Hsu

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/45

Abstract: A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.

公开(公告)号：US20190252035A1

公开(公告)日：2019-08-15

申请号：US16393982

申请日：2019-04-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G11C29/52 ,  G06F11/10 ,  G11C29/02 ,  H03M13/29 ,  G11C29/42

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2963

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: arranging a plurality of first voltage levels which are used continuously for reading first data from a plurality of first memory cells according to a first wear degree of the first memory cells; decoding the first data which is read by the arranged first voltage levels; arranging a plurality of second voltage levels which are used continuously for reading second data from the first memory cells according to a second wear degree of the first memory cells, wherein the first wear degree of the first memory cells is different from the second wear degree of the first memory cells, and a voltage gap between any two neighboring voltages levels among the first voltage levels is different from a voltage gap between any two neighboring voltage levels among the second voltage levels; and decoding the second data which is read by the arranged second voltage levels.