公开(公告)号：US20150155250A1

公开(公告)日：2015-06-04

申请号：US14143700

申请日：2013-12-30

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Tzu-Chieh Chen ,  Shih-Chao Chiu ,  Chia-Cheng Chen

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L24/32 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility.

Abstract translation: 提供一种半导体封装，其包括：具有相对的第一和第二表面的第一介电层和穿透第一表面和第二表面的空腔; 第一电路层，其被嵌入在所述第一电介质层中并从所述第一介电层的所述第一表面露出; 至少形成在所述空腔中并且与所述第一介电层的所述第一表面相邻的粘合构件; 设置在所述粘合构件上的电子元件; 第二电介质层，形成在所述第一介电层的所述第二表面上并且在所述空腔中，以封装所述粘合剂构件和所述电子元件; 形成在所述第二电介质层上的第二电路层; 以及形成在第二电介质层中的多个导电通孔，用于电连接第二电路层和电子元件，由此减小封装尺寸和成本并增加布线空间和柔性。

公开(公告)号：US10002825B2

公开(公告)日：2018-06-19

申请号：US15625083

申请日：2017-06-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/538 ,  H05K3/00 ,  H01L21/683 ,  H05K3/32 ,  H05K3/10 ,  H01L23/00 ,  H05K1/02 ,  H05K3/46 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US20170352615A1

公开(公告)日：2017-12-07

申请号：US15625083

申请日：2017-06-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L23/538 ,  H05K3/32 ,  H05K3/00 ,  H05K1/18 ,  H01L21/683 ,  H05K3/46 ,  H01L23/00 ,  H01L23/31 ,  H05K1/02 ,  H05K3/10

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US20170301658A1

公开(公告)日：2017-10-19

申请号：US15636217

申请日：2017-06-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H05K1/111 ,  H05K3/4697 ,  H05K2201/10674

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.

公开(公告)号：US09735080B2

公开(公告)日：2017-08-15

申请号：US14876404

申请日：2015-10-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49861 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

公开(公告)号：US09490225B2

公开(公告)日：2016-11-08

申请号：US14452731

申请日：2014-08-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wei-Chung Hsiao ,  Chun-Hsien Lin ,  Yu-cheng Pai ,  Ming-Chen Sun ,  Shih-Chao Chiu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure is provided, which includes: a substrate having opposite top and bottom surfaces and a plurality of conductive pads and a plurality of conductive posts formed therein, wherein the conductive pads are exposed from the bottom surface of the substrate, and the conductive posts are electrically connected to the conductive pads and each of the conductive posts has an end surface exposed from the top surface of the substrate; a plurality of first conductive bumps formed on the end surfaces of the conductive posts; a plurality of second conductive bumps formed on the top surface of the substrate, wherein the second conductive bumps are higher than the first conductive bumps; and at least a first electronic element disposed on and electrically connected to the first conductive bumps, thereby increasing the wiring flexibility and facilitating subsequent disposing of electronic elements without changing existing machines.

Abstract translation: 提供了一种封装结构，其包括：具有相对的顶表面和底表面的衬底和形成在其中的多个导电焊盘和多个导电柱，其中，导电焊盘从衬底的底表面露出，导电柱 电连接到导电焊盘，并且每个导电柱具有从衬底的顶表面暴露的端表面; 形成在所述导电柱的端面上的多个第一导电凸块; 形成在所述基板的上表面上的多个第二导电凸块，其中所述第二导电凸块高于所述第一导电凸块; 以及至少第一电子元件，其设置在第一导电凸块上并与之电连接，从而增加布线灵活性，并且便于随后处理电子元件而不改变现有机器。

公开(公告)号：US20160155716A1

公开(公告)日：2016-06-02

申请号：US14837245

申请日：2015-08-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ming-Chen Sun ,  Chun-Hsien Lin ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Yu-Cheng Pai

IPC: H01L23/00 ,  H01L21/56 ,  H05K3/00 ,  H05K3/10 ,  H05K3/40 ,  H01L23/31 ,  H05K1/11

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2924/15313 ,  H05K1/111 ,  H05K3/20 ,  H05K3/205 ,  H05K3/428 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

Abstract translation: 提供封装基板和半导体封装。 封装衬底包括具有相对的第一和第二表面的绝缘层; 形成在绝缘层中的第一布线层，从绝缘层的第一表面露出并具有多个第一导电焊盘; 形成在所述绝缘层中的第二布线层，从所述第二表面露出并具有多个第二导电焊盘; 第三布线层，形成在第一表面上并与第一布线层电连接; 形成在所述第一导电焊盘上的多个第一金属凸块对应; 以及垂直嵌入绝缘层中并与第二和第三布线层电连接的至少一个导电通孔。 因此，第一导电焊盘的表面被减小，并且避免了第一导电焊盘和形成在导电凸块上的焊料材料之间的不润湿。

公开(公告)号：US20160093546A1

公开(公告)日：2016-03-31

申请号：US14833102

申请日：2015-08-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Shih-Chao Chiu ,  Chun-Hsien Lin ,  Chih-Wen Fan ,  Cheng-Chia Chen

IPC: H01L23/13 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/37001 ,  H05K3/4682 ,  H05K2203/0152 ,  H05K2203/016 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a package structure is provided. The method includes providing a carrier having two opposing surfaces, forming dielectric bodies on the two surfaces of the carrier, respectively, each of the dielectric bodies having a wiring layer embedded therein and a conductive layer formed on the wiring layer, and removing the carrier. Therefore, the wiring layers, the conductive layers and the dielectric bodies are formed on the two surfaces of the carrier, respectively, and the production yield is thus increased. The present invention further provides the package structure thus fabricated.

Abstract translation: 提供一种制造封装结构的方法。 该方法包括提供具有两个相对表面的载体，分别在载体的两个表面上形成介电体，每个绝缘体具有嵌入其中的布线层和形成在布线层上的导电层，并且去除载体。 因此，分别在载体的两个表面上形成布线层，导电层和介电体，从而提高了生产量。 本发明还提供如此制造的封装结构。

公开(公告)号：US20160086879A1

公开(公告)日：2016-03-24

申请号：US14805524

申请日：2015-07-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ming-Chen Sun ,  Chun-Hsien Lin ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Yu-Cheng Pai

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K3/0038 ,  H01L2924/00

Abstract: A package substrate includes a substrate body having a first surface and a second surface opposite to the first surface; a first circuit layer formed on the first surface and having first conductive pads; a first dielectric layer formed on the first surface and the first circuit; a second circuit layer formed on the first dielectric layer and having second conductive pads; a third circuit layer formed on the second surface and having third conductive pads; a second dielectric layer formed on the second surface and the third circuit layer; a fourth circuit layer formed on the second dielectric layer and having fourth conductive pads; through holes penetrating through the first and second surfaces, and the first and second dielectric layers; and conductive vias penetrating through the through holes and electrically connected to the first, second, third and fourth conductive pads.

Abstract translation: 封装衬底包括具有第一表面和与第一表面相对的第二表面的衬底本体; 形成在第一表面上并具有第一导电焊盘的第一电路层; 形成在第一表面和第一电路上的第一电介质层; 形成在所述第一电介质层上并具有第二导电焊盘的第二电路层; 形成在所述第二表面上并具有第三导电焊盘的第三电路层; 形成在所述第二表面和所述第三电路层上的第二电介质层; 形成在所述第二电介质层上并具有第四导电焊盘的第四电路层; 穿透第一和第二表面的穿透孔以及第一和第二介电层; 以及穿过通孔并电连接到第一，第二，第三和第四导电焊盘的导电通孔。

公开(公告)号：US09899249B2

公开(公告)日：2018-02-20

申请号：US15334569

申请日：2016-10-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L21/683 ,  H05K3/40 ,  H01L23/498 ,  H01L21/48 ,  H05K3/46 ,  H05K3/20 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.