公开(公告)号：US20180012772A1

公开(公告)日：2018-01-11

申请号：US15678134

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US09673053B2

公开(公告)日：2017-06-06

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

公开(公告)号：US09466535B2

公开(公告)日：2016-10-11

申请号：US14636940

申请日：2015-03-03

Applicant: United Microelectronics Corp.

Inventor： Po-Cheng Huang ,  Kun-Ju Li ,  Yu-Ting Li ,  Chih-Hsun Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/306

CPC classification number: H01L21/823437 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.

Abstract translation: 公开了形成目标图案的方法。 提供具有多个散热片的基板。 在鳍片和非目标区域的至少一部分中形成多个掩模图案。 目标图案分别形成在掩模图案之间的沟槽中。 去除掩模图案。 利用所公开的方法，可以以基本相等的厚度形成目标图案。 在目标图案是伪栅极的情况下，在虚拟栅极去除步骤中没有观察到由不均匀厚度引起的诸如伪栅极残留或栅极沟槽加宽的常规缺陷。

公开(公告)号：US20160260637A1

公开(公告)日：2016-09-08

申请号：US14636940

申请日：2015-03-03

Applicant: United Microelectronics Corp.

Inventor： Po-Cheng Huang ,  Kun-Ju Li ,  Yu-Ting Li ,  Chih-Hsun Lin

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.

Abstract translation: 公开了形成目标图案的方法。 提供具有多个散热片的基板。 在鳍片和非目标区域的至少一部分中形成多个掩模图案。 目标图案分别形成在掩模图案之间的沟槽中。 去除掩模图案。 利用所公开的方法，可以以基本相等的厚度形成目标图案。 在目标图案是伪栅极的情况下，在虚拟栅极去除步骤中没有观察到由不均匀厚度引起的诸如伪栅极残留或栅极沟槽加宽的常规缺陷。

公开(公告)号：US20160013100A1

公开(公告)日：2016-01-14

申请号：US14461433

申请日：2014-08-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Po-Cheng Huang ,  Chih-Chien Liu ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chang-Hung Kung ,  Wen-Chin Lin ,  Chih-Hsun Lin ,  Kuo-Chin Hung

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/32136 ,  H01L21/3215 ,  H01L21/76859 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A via structure and a method of forming the same are provided. In the forming method of the present invention, a via is formed in a dielectric layer. Next, a U-shaped seed layer is formed in the via. After that, a conductive material is selectively formed in the via to form a conductive bulk layer in the via. Through the present invention, the purposes of effectively removing the overhang adjacent to the opening of the via and protecting the U-shaped seed layer in the via can be achieved.

Abstract translation: 提供通孔结构及其形成方法。 在本发明的形成方法中，在电介质层中形成通孔。 接下来，在通孔中形成U形种子层。 之后，在通路中选择性地形成导电材料，以在通孔中形成导电体层。 通过本发明，可以实现有效地去除邻近通孔开口的突出端并保护通孔中的U形种子层的目的。

公开(公告)号：US20250166997A1

公开(公告)日：2025-05-22

申请号：US18537814

申请日：2023-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ping Wang ,  Chuan-Lan Lin ,  Chu-Fu Lin ,  Teng-Chuan Hu ,  Kun-Ju Li

IPC: H01L21/304 ,  H01L21/3065 ,  H01L23/00 ,  H01L25/065

Abstract: The invention provide an edge structure of a semiconductor wafer, which comprise a first substrate, an edge region and a device region are defined on that first substrate, a first material layer covers a first surface and a side surface of the edge region, and a second material layer covers the first material layer, the cross-sectional structure of the second material layer gradually decreases from the device region to the edge region.

公开(公告)号：US20230354715A1

公开(公告)日：2023-11-02

申请号：US18215162

申请日：2023-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80

CPC classification number: H10N50/10 ,  H01L21/76802 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

公开(公告)号：US11737370B2

公开(公告)日：2023-08-22

申请号：US17141194

申请日：2021-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L41/47 ,  H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

CPC classification number: H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

公开(公告)号：US11621296B2

公开(公告)日：2023-04-04

申请号：US17223024

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H01L29/82 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

公开(公告)号：US20230051000A1

公开(公告)日：2023-02-16

申请号：US17494809

申请日：2021-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ang Chan ,  Hsin-Jung Liu ,  Kun-Ju Li ,  Chau-Chung Hou ,  Fu-Shou Tsai ,  Yu-Lung Shih ,  Jhih-Yuan Chen ,  Chun-Han Chen ,  Wei-Xin Gao ,  Shih-Ming Lin

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion connecting the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, and a dummy via through the second dielectric layer and directly contacting the terminal portion. In a cross-sectional view, a width of the dummy via is smaller than 50% of a width of the conductive via.