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    GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS
    21.
    发明申请
    GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS 审中-公开

    公开(公告)号：US20200251167A1

    公开(公告)日：2020-08-06

    申请号：US16784332

    申请日：2020-02-07

    Applicant: Unity Semiconductor Corporation

    Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

    IPC: G11C13/00 ,  H01L27/10 ,  G11C5/06 ,  G11C7/18 ,  G11C5/08 ,  G11C7/12 ,  G11C16/24 ,  G11C7/00 ,  G11C7/04

    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
    22.
    发明授权
    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations 有权

    公开(公告)号：US10566056B2

    公开(公告)日：2020-02-18

    申请号：US16297303

    申请日：2019-03-08

    Applicant: Unity Semiconductor Corporation

    Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

    IPC: G11C11/00 ,  G11C13/00 ,  G11C7/04 ,  G11C7/00 ,  G11C16/24 ,  G11C7/12 ,  G11C5/08 ,  G11C7/18 ,  G11C5/06

    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
    23.
    发明授权
    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations 有权

    公开(公告)号：US10229739B2

    公开(公告)日：2019-03-12

    申请号：US15868234

    申请日：2018-01-11

    Applicant: Unity Semiconductor Corporation

    Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

    IPC: G11C11/00 ,  G11C13/00 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/18 ,  G11C7/04 ,  G11C7/12 ,  G11C16/24

    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

    VERTICAL GATE NAND MEMORY DEVICES
    25.
    发明申请
    VERTICAL GATE NAND MEMORY DEVICES 有权
    垂直门NAND存储器件

    公开(公告)号：US20150014760A1

    公开(公告)日：2015-01-15

    申请号：US14314622

    申请日：2014-06-25

    Applicant: Unity Semiconductor Corporation

    Inventor： Bruce Lynn Bateman

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926

    Abstract: In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line.

    Abstract translation: 在一个示例中，设备包括垂直堆叠的存储器单元。 垂直堆栈的每个存储单元可以包括多于一个存储元件。 第一垂直栅极线可以耦合到每个存储器单元中的存储器元件中的第一个，并且第二垂直栅极线可以耦合到每个存储器单元中的第二个存储器元件。 第一垂直栅极线可以与第二垂直栅极线电隔离。

    VERTICAL CROSS-POINT MEMORY ARRAYS
    27.
    发明申请
    VERTICAL CROSS-POINT MEMORY ARRAYS 审中-公开

    公开(公告)号：US20200258940A1

    公开(公告)日：2020-08-13

    申请号：US16735394

    申请日：2020-01-06

    Applicant: Unity Semiconductor Corporation

    Inventor： Lidia Vereen ,  Bruce Lynn Bateman ,  David Alan Eggleston ,  Louis C. Parrillo

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

    Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    VERTICAL CROSS-POINT ARRAYS FOR ULTRA-HIGH-DENSITY MEMORY APPLICATIONS
    28.
    发明申请
    VERTICAL CROSS-POINT ARRAYS FOR ULTRA-HIGH-DENSITY MEMORY APPLICATIONS 审中-公开

    公开(公告)号：US20180012934A1

    公开(公告)日：2018-01-11

    申请号：US15633050

    申请日：2017-06-26

    Applicant: Unity Semiconductor Corporation

    Inventor： Bruce Lynn Bateman

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2 F2 may be realized.

    Vertical cross-point arrays for ultra-high-density memory applications
    30.
    发明授权
    Vertical cross-point arrays for ultra-high-density memory applications 有权

    公开(公告)号：US09691821B2

    公开(公告)日：2017-06-27

    申请号：US15095542

    申请日：2016-04-11

    Applicant: Unity Semiconductor Corporation

    Inventor： Bruce Lynn Bateman

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/249 ,  H01L27/2418 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

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