公开(公告)号：US20090026599A1

公开(公告)日：2009-01-29

申请号：US11878891

申请日：2007-07-27

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/02

CPC classification number: H05K1/0271 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H05K1/181 ,  H05K2201/09145 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2201/2009 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A memory module capable of lessening shock stresses, primarily comprises a multi-layer printed circuit board (PCB), a plurality of memory packages, and a stress-buffering layer. The memory packages are disposed at least on one of the rectangular surfaces of the PCB. The stress-buffering layer is disposed at least on both short sides of the PCB and extended to the two rectangular surfaces to reduce the impact stresses. Preferably, the stress-buffering layer is further disposed on the other long side of the PCB opposite to the one with disposed gold fingers.

Abstract translation: 能够减轻冲击应力的存储器模块主要包括多层印刷电路板（PCB），多个存储器封装和应力缓冲层。 存储器封装被布置在PCB的至少一个矩形表面上。 应力缓冲层至少设置在PCB的两个短边上并延伸到两个矩形表面以减小冲击应力。 优选地，应力缓冲层进一步设置在PCB的与设置的金手指相对的另一长边上。

公开(公告)号：US20080179731A1

公开(公告)日：2008-07-31

申请号：US11657715

申请日：2007-01-25

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/13

CPC classification number: H05K1/0271 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H05K1/117 ,  H05K2201/09909 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2201/2009 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An anti-impact memory module mainly comprises a multi-layer PWB (Printed Wiring Board), a plurality of memory packages and a plurality of first anti-impact bars. The PWB has two longer sides and two shorter sides. A plurality of gold fingers are disposed along one of the longer sides. The first anti-impact bars are disposed on one surface of the PWB and adjacent to the two shorter sides, which are higher than the memory packages in height. Preferably, at least a second anti-impact bar is formed at another longer side far away from the gold fingers. The first anti-impact bars and/or the second anti-impact bar can be utilized to cushion impact force for preventing the memory module product from damaging while fallen accidentally.

Abstract translation: 防冲击存储器模块主要包括多层PWB（印刷线路板），多个存储器封装和多个第一抗冲击棒。 电路板有两个长边和两个短边。 多个金指沿着较长的一侧设置。 第一个防冲击杆设置在PWB的一个表面上，并且与两个短边相邻，这两个较短的边比高度的存储包高。 优选地，至少第二防撞杆形成在远离金手指的另一较长侧。 第一防冲击杆和/或第二防冲击杆可以用于缓冲冲击力，以防止存储模块产品在意外下降时受到损坏。

公开(公告)号：US20080054494A1

公开(公告)日：2008-03-06

申请号：US11514349

申请日：2006-09-01

Applicant: Cheng-Ping Chen ,  Wen-Jeng Fan

Inventor： Cheng-Ping Chen ,  Wen-Jeng Fan

IPC: H01L23/28

CPC classification number: H01L23/3128 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An IC package mainly includes a substrate having slot(s), a chip, a protective encapsulant, a stiffening encapsulant, and a plurality of external terminals. The Young's modulus of the stiffening encapsulant is greater than the one of the protective encapsulant and the curing shrinkage of the stiffening encapsulant is smaller than the one of the protective encapsulant. The protective encapsulant is formed on one of the surfaces of the substrate for encapsulating the chip. The stiffening encapsulant protrudes from the other surface of the substrate where the external terminals are disposed. Moreover, the stiffening encapsulant is formed inside the slot and is contacted with the chip. Since the stiffening encapsulant is embedded and formed inside the slot, therefore, the contact area of the stiffening encapsulant with the substrate is increased to enhance the warpage resistance of the IC package.

Abstract translation: IC封装主要包括具有槽的衬底，芯片，保护性密封剂，加强密封剂和多个外部端子。 加强密封剂的杨氏模量大于保护性密封剂中的一种，并且硬化密封剂的固化收缩率小于保护性密封剂中的一种。 保护性密封剂形成在用于封装芯片的衬底的一个表面上。 加强密封剂从设置有外部端子的基板的另一个表面突出。 此外，加强密封剂形成在槽内并与芯片接触。 由于加强密封剂嵌入并形成在槽内，因此，加强密封剂与基板的接触面积增大，以提高IC封装的翘曲阻力。

公开(公告)号：US08049339B2

公开(公告)日：2011-11-01

申请号：US12276970

申请日：2008-11-24

Applicant: Wen-Jeng Fan ,  Yu-Mei Hsu

Inventor： Wen-Jeng Fan ,  Yu-Mei Hsu

IPC: H01L23/48

CPC classification number: H01L23/4951 ,  H01L23/4952 ,  H01L23/49558 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip. A jumping wire electrically connecting the isolated inner lead and the external lead is adjacent to the second side to achieve the redistribution of pin assignments without affecting wire-bonding. Especially, this package can be applied for multi-chip stacking.

Abstract translation: 揭示了具有隔离内部引线的半导体封装。 芯片设置在引线框架段上并由密封剂封装。 引线框架段包括多个引线，隔离引线和外部引线，其中每个引线具有内部部分和外部部分。 隔离的内部引线完全形成在密封剂内部，外部引线部分地形成在密封剂内部并延伸到密封剂外部。 引线的内部部分中的至少一个位于隔离的内引线和外引线之间。 两个指状物形成在隔离的内部引线的两个相对的端部，而不被芯片覆盖。 手指中的一个模仿引线的多个指状物沿着芯片的第一侧布置。 隔离的内部引线的另一个手指和外部引线的手指沿芯片的第二侧布置。 将隔离的内部引线和外部引线电连接的跳线与第二侧相邻，以实现引脚分配的重新分配，而不影响引线接合。 特别地，该封装可以应用于多芯片堆叠。

公开(公告)号：US07972904B2

公开(公告)日：2011-07-05

申请号：US12423456

申请日：2009-04-14

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L21/00

CPC classification number: H01L23/544 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L2223/54453 ,  H01L2224/83856 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A wafer level packaging method is revealed. Firstly, a wafer with a plurality of bumps disposed on a surface is provided. Placing a dielectric tape on a mold plate is followed. Then, the wafer is laminated with the mold plate to make the dielectric tape be compliantly bonded to the surface of the wafer and to make the bumps be embedded in the dielectric tape. After removing the mold plate, flattening the dielectric tape to form a plurality of exposed surfaces of the bumps wherein the exposed surfaces and the flattened surface of the dielectric tape are coplanar. Therefore, the exposed surfaces of the bumps can be regarded as effective alignment points for easy pattern recognition of the wafer level packaged wafers during singulation process.

Abstract translation: 揭示了晶圆级封装方法。 首先，提供具有设置在表面上的多个凸块的晶片。 跟随介质胶带放在模板上。 然后，将晶片与模板层压，使介质带顺从地结合到晶片的表面，并使凸块嵌入电介质带中。 在去除模板之后，使介质带平坦化以形成凸起的多个暴露表面，其中介电带的暴露表面和扁平表面是共面的。 因此，可以将凸起的露出表面视为有效对准点，以便在切割过程中容易地对晶片级封装晶片进行图案识别。

公开(公告)号：US07927919B1

公开(公告)日：2011-04-19

申请号：US12630623

申请日：2009-12-03

Applicant: Wen-Jeng Fan ,  Li-Chih Fang ,  Ronald Takao Iwata

Inventor： Wen-Jeng Fan ,  Li-Chih Fang ,  Ronald Takao Iwata

IPC: H01L21/00

CPC classification number: H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/731 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor packaging method without an interposer is revealed. A mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage.

Abstract translation: 揭示了没有插入器的半导体封装方法。 母芯片是由半导体层和有机层组成的两层结构，其中再分布层被嵌入到有机层中，多个第一端子和多个第二端子设置在再分配层上并从有机层暴露出来 层。 母芯片倒装芯片安装在基板上。 子芯片的有源面与有机层接触，子芯片的接合焊盘与第一端子接合。 此外，多个电连接部件将第二端子电连接到基板。 在多芯片堆叠封装中，可以以更薄的整体封装厚度以及受控的封装翘曲消除中介层。

公开(公告)号：US07919715B2

公开(公告)日：2011-04-05

申请号：US12123269

申请日：2008-05-19

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H05K1/11

CPC classification number: H05K3/242 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/11 ,  H05K3/0044 ,  H05K2201/09063 ,  H05K2203/175 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuit substrate ready to slot is revealed, primarily comprising a board base with slot-reserved area. A plurality of bonding fingers, a plating bus loop, and a plurality of plating lines disposed on the bottom surface of the board base. The bonding fingers are located adjacent to but outside the slot-reserved area and the plating bus loop is located inside the slot-reserved area. The plating lines connect the bonding fingers to the plating bus lines. The plating bus loop includes two side bars closer to the long sides of the slot-reserved area than the bonding fingers to the long sides. Accordingly, the lengths of the plating lines within the slot-reserved area are shortened. It is possible to solve the issues of metal burs and shifting of the remaining plating lines when routing a slot along the peripheries of the slot-reserved area. Moreover, the plating current can evenly distribute to improve the plating qualities on the surfaces of the bonding fingers.

Abstract translation: 显示准备插槽的电路基板，主要包括具有槽保留区域的板基座。 多个接合指状物，电镀母线回路以及设置在基板底面上的多条电镀线。 接合指状物位于槽保留区域附近，并且电镀总线环路位于槽保留区域内。 电镀线将接合指状物连接到电镀母线。 电镀总线回路包括两个靠近槽保留区域的长边的两个侧杆，而不是指向长边的接合指。 因此，槽保留区域内的电镀线的长度缩短。 当沿着槽保留区域的周边布置槽时，可以解决金属毛刺的问题和剩余电镀线的移位。 此外，电镀电流可以均匀分布，以提高接合指的表面上的电镀质量。

公开(公告)号：US07667306B1

公开(公告)日：2010-02-23

申请号：US12269543

申请日：2008-11-12

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/49513 ,  H01L23/49551 ,  H01L23/49555 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/8388 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A leadframe-based semiconductor package is revealed, primarily comprising a chip, a plurality of leads of a leadframe, a multi-layer tape, and an encapsulant. The multi-layer tape is attached to the chip and includes an adhesive layer disposed on a dielectric core layer. The internal leads of the leads are partially embedded in the adhesive layer in a manner not to directly contact the dielectric core layer. A bonding interface with a U-shaped profile is formed between the adhesive layer and each internal lead to increase the adhesions of the leads so that the internal leads will not be shifted nor delaminated during molding processes. The concentrated stresses exerted on the internal leads disposed at the corners of the packages will be released and reduced.

Abstract translation: 揭示了基于引线框的半导体封装，主要包括芯片，引线框的多个引线，多层带和密封剂。 多层带附着到芯片上，并且包括设置在介电芯层上的粘合剂层。 引线的内部引线以不直接接触介电芯层的方式部分地嵌入粘合剂层中。 在粘合剂层和每个内部引线之间形成具有U形轮廓的接合界面，以增加引线的粘连，使得内部引线在模制过程中不会移动或分层。 施加在设置在包装角落处的内部引线上的集中应力将被释放和减少。

公开(公告)号：US20090227048A1

公开(公告)日：2009-09-10

申请号：US12042093

申请日：2008-03-04

Applicant: Li-Chih FANG ,  Wen-Jeng Fan ,  Nan-Chun Lin

Inventor： Li-Chih FANG ,  Wen-Jeng Fan ,  Nan-Chun Lin

IPC: H01L21/66

CPC classification number: H01L21/67144 ,  H01L21/67271

Abstract: Disclosed is a die-bonding method having pick-and-probe features after wafer sawing where at least a die is probed and sorted according to different grades during a pick-and-place step performed after wafer sawing. A suction nozzle having a plurality of probes is utilized to probe the electrical terminals of the die. After picking, the suction nozzle is moved on a common moving path and the picked die is tested through the suction nozzle. The picked-and-probed die is moved and die-bonded to a die carrier loaded in a corresponding one of a plurality of die-bonding areas by moving the Suction nozzle on a chosen sorting path. Therefore, the die is probed and sorted during die-bonding processes. Higher graded dice at a same level are assembled on a same die carrier to form a higher graded semiconductor package.

Abstract translation: 公开了一种在晶片锯切之后具有拾取和探针特征的芯片接合方法，其中在晶片锯切之后执行的拾取和放置步骤期间，至少一个模具被探测并根据不同的等级进行分类。 使用具有多个探针的吸嘴来探测管芯的电端子。 拾取后，吸嘴在公共移动路径上移动，并通过吸嘴测试拾取的模具。 通过在所选择的分选路径上移动吸入喷嘴，将拾取和探测的模具移动并压模到装载在多个芯片接合区域中的相应的一个芯片接合区域中的模具载体。 因此，在芯片接合工艺期间探针和分选。 相同级别的较高分级骰子组装在相同的裸片载体上以形成更高级别的半导体封装。

公开(公告)号：US07569935B1

公开(公告)日：2009-08-04

申请号：US12269577

申请日：2008-11-12

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L29/40

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L21/565 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2224/05099

Abstract: A pillar-to-pillar flip-chip assembly primarily comprises a substrate, a chip disposed on the substrate, a plurality of first copper pillars on the bonding pads of the chip, a plurality of second copper pillars on the bump pads of the substrate, and a soldering material. A first height of the first copper pillars protruding from the active surface of the chip is the same as a second height of the second copper pillars from the solder mask on the substrate. When the soldering material electrically and mechanically connects the first copper pillars to the second copper pillars, a plurality of central points of the soldering material are formed on an equal-dividing plane between the chip and the substrate to reduce the direct stresses exerted at the soldering material to avoid peeling or breaks from the bump pads. Moreover, each of conventional solder balls is replaced with two soldered copper pillars to meet the lead-free requirements with higher reliability and lower costs.

Abstract translation: 柱对倒装芯片组件主要包括衬底，设置在衬底上的芯片，在芯片的焊盘上的多个第一铜柱，衬底的凸块焊盘上的多个第二铜柱， 和焊接材料。 从芯片的有源表面突出的第一铜柱的第一高度与来自衬底上的焊接掩模的第二铜柱的第二高度相同。 当焊接材料将第一铜柱与第二铜柱电气和机械连接时，焊料的多个中心点形成在芯片和基板之间的等分平面上，以减少焊接时施加的直接应力 材料以避免从凸点焊盘剥落或断裂。 此外，每个常规焊球都被两个焊接的铜柱替代，以满足无铅要求，具有更高的可靠性和更低的成本。