公开(公告)号：US12272645B2

公开(公告)日：2025-04-08

申请号：US17738786

申请日：2022-05-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei Liu ,  Yuancheng Yang ,  Wenxi Zhou ,  Kun Zhang ,  Di Wang ,  Tao Yang ,  Dongxue Zhao ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B12/00 ,  H01L23/528 ,  H10B41/20 ,  H10B43/20

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

公开(公告)号：US20250089235A1

公开(公告)日：2025-03-13

申请号：US18374524

申请日：2023-09-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue Zhao ,  Yuancheng Yang ,  Tao Yang ,  Changzhi Sun ,  Wei Liu ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/786

Abstract: Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises a plurality of vertical transistors, each comprising: a semiconductor layer having a leakage value lower than a pico-ampere and comprising a vertical semiconductor portion and at least one lateral semiconductor portion, a gate dielectric layer comprising a vertical gate dielectric portion on the vertical semiconductor portion and extending in the vertical direction, a gate electrode on the gate dielectric layer and separated from the semiconductor layer by the gate dielectric layer. The disclosed semiconductor device further comprises a plurality of capacitors each coupled with the semiconductor layer of a corresponding one of the plurality of vertical transistors.

公开(公告)号：US20250016985A1

公开(公告)日：2025-01-09

申请号：US18888331

申请日：2024-09-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B12/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L29/66 ,  H01L29/78

Abstract: A memory device includes a vertical transistor including a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The memory device further includes a storage unit coupled to one of the source and the drain, a word line extending in a second direction perpendicular to the first direction, and a body line coupled to the channel portion of the semiconductor body. The word line is between the storage unit and the body line in the first direction.

公开(公告)号：US20240292629A1

公开(公告)日：2024-08-29

申请号：US18296182

申请日：2023-04-05

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Dongxue Zhao ,  Tao Yang ,  Wenxi Zhou ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B53/20 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B53/30 ,  H10B80/00

CPC classification number: H10B53/20 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B53/30 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1441

Abstract: Embodiments of 3D memory devices and methods for forming the 3D memory device are disclosed. In one example, a 3D memory device includes a memory array and a peripheral circuit bonded to the memory array. The memory array includes a first multi-layer stacked structure, first capacitor structures penetrating the first multi-layer stacked structure, and a blocking structure penetrating the first multi-layer stacked structure. The first multi-layer stacked structure includes alternately stacked dielectric layers and conductive layers. Each of the first capacitor structures includes a dielectric layer and an electrode layer, where the dielectric layer of a first capacitor structure is disposed between the electrode layer of the first capacitor structure and the dielectric layers or the conductive layers of the first multi-layer stacked structure. The blocking structure separates one subset of the first capacitor structures from another subset of the first capacitor structures.

公开(公告)号：US20240215235A1

公开(公告)日：2024-06-27

申请号：US18092777

申请日：2023-01-03

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Zongliang Huo

IPC: H10B41/40 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40

Abstract: A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a pad-out structure disposed on the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal in contact with the first side of the first semiconductor layer and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; and a plate line extending in the second direction.

公开(公告)号：US20240212753A1

公开(公告)日：2024-06-27

申请号：US18095336

申请日：2023-01-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Zongliang Huo

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.

公开(公告)号：US20230361030A1

公开(公告)日：2023-11-09

申请号：US17738715

申请日：2022-05-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yuancheng Yang ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/528 ,  H01L27/11578 ,  H01L27/11551

CPC classification number: H01L23/5283 ,  H01L27/11578 ,  H01L27/11551

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a memory stack on the bottom conductive layer, the memory stack comprising a plurality of alternatively arranged dielectric layers and conductive layers; forming an opening penetrating the memory stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and forming a plurality of interconnection structures to electrically connect the bottom conductive layer, the plurality of conductive layers of the memory stack, and the top contact.

公开(公告)号：US20230138205A1

公开(公告)日：2023-05-04

申请号：US17539784

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on all sides of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

公开(公告)号：US20230133595A1

公开(公告)日：2023-05-04

申请号：US17539742

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, a bit line, and a body line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and coupled to a second terminal. The second terminal is another one of the source and the drain. The body line is coupled to the channel portion of the semiconductor body.