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公开(公告)号：US07282383B2
公开(公告)日：2007-10-16
申请号：US10864841
申请日：2004-06-09
Applicant: Yuichi Yamamoto
Inventor： Yuichi Yamamoto
IPC: H01L21/302
CPC classification number: B81C1/00611 , B81B2201/0271 , B81C2201/0125 , H03H3/0072
Abstract: In a production method of a micromachine having a space between first and second electrodes, a first electrode is formed on a substrate, and then a stopper film is formed on its surface. Next, a second insulating film is formed as to cover the stopper film. The thickness of the second insulating film is larger than a total thickness of the first electrode and stopper film. Then, second insulating film is polished. By this polishing, the stopper film is exposed to the outside to the outside, and is planarized. After forming an opening in the stopper film, a sacrifice film is burred in the opening. Surfaces of the sacrifice film and second insulating film are planarized, and a second electrode is formed on the second insulating film as to cross the sacrifice film. A space is formed between the first and second electrodes by removing the sacrifice film.
Abstract translation: 在具有在第一和第二电极之间具有空间的微加工机的制造方法中，在基板上形成第一电极，然后在其表面上形成止动膜。 接下来，形成第二绝缘膜以覆盖止动膜。 第二绝缘膜的厚度大于第一电极和阻挡膜的总厚度。 然后，对第二绝缘膜进行抛光。 通过该抛光，将止动膜暴露在外部至外部，并进行平坦化。 在阻挡膜中形成开口后，在开口中将牺牲膜烧结。 牺牲膜和第二绝缘膜的表面被平坦化，并且第二电极形成在第二绝缘膜上以与牺牲膜交叉。 通过去除牺牲膜在第一和第二电极之间形成空间。
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公开(公告)号：US20050003566A1
公开(公告)日：2005-01-06
申请号：US10864841
申请日：2004-06-09
Applicant: Yuichi Yamamoto
Inventor： Yuichi Yamamoto
CPC classification number: B81C1/00611 , B81B2201/0271 , B81C2201/0125 , H03H3/0072
Abstract: In a production method of a micromachine having a space between first and second electrodes, a first electrode is formed on a substrate, and then a stopper film is formed on its surface. Next, a second insulating film is formed as to cover the stopper film. The thickness of the second insulating film is larger than a total thickness of the first electrode and stopper film. Then, second insulating film is polished. By this polishing, the stopper film is exposed to the outside to the outside, and is planarized. After forming an opening in the stopper film, a sacrifice film is burred in the opening. Surfaces of the sacrifice film and second insulating film are planarized, and a second electrode is formed on the second insulating film as to cross the sacrifice film. A space is formed between the first and second electrodes by removing the sacrifice film.
Abstract translation: 在具有在第一和第二电极之间具有空间的微加工机的制造方法中，在基板上形成第一电极，然后在其表面上形成止动膜。 接下来，形成第二绝缘膜以覆盖止动膜。 第二绝缘膜的厚度大于第一电极和阻挡膜的总厚度。 然后，对第二绝缘膜进行抛光。 通过该抛光，将止动膜暴露在外部至外部，并进行平坦化。 在阻挡膜中形成开口后，在开口中将牺牲膜烧结。 牺牲膜和第二绝缘膜的表面被平坦化，并且第二电极形成在第二绝缘膜上以与牺牲膜交叉。 通过去除牺牲膜在第一和第二电极之间形成空间。
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23.发明授权
公开(公告)号：US5919548A
公开(公告)日：1999-07-06
申请号：US915071
申请日：1997-08-20
Applicant: Carole C. Barron , Dale L. Hetherington , Stephen Montague
Inventor： Carole C. Barron , Dale L. Hetherington , Stephen Montague
CPC classification number: B81C1/00611 , B81C2201/0125 , Y10T428/24331
Abstract: A method is disclosed for micromachining recessed layers (e.g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e.g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e.g. CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate.
Abstract translation: 公开了一种用于微加工在蚀刻到半导体衬底中的腔体中形成的微机电系统（MEMS）器件的凹陷层（例如，牺牲层）的方法。 该方法使用具有弹性抛光垫的化学机械抛光（CMP）来在衬底腔内局部平坦化一个或多个凹陷层。 使用本发明的方法的这种局部平面化有利于改进随后沉积的层的图案化，以消除MEMS器件的功能元件（例如，连接）之间的机械干扰，并且用于消除桁条的形成。 在一个或多个凹陷层的局部平坦化之后，可以提供另一个CMP步骤用于全面平坦化半导体衬底以形成凹陷的MEMS器件，该MEMS器件可与形成在其上的凹陷的MEMS器件集成在电子电路（例如，CMOS，BiCMOS或双极电路） 基板的表面。
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公开(公告)号：US20240109769A1
公开(公告)日：2024-04-04
申请号：US18538503
申请日：2023-12-13
Applicant: Xintec Inc.
Inventor： Wei-Luen SUEN , Jiun-Yen LAI , Hsing-Lung SHEN , Tsang-Yu LIU
CPC classification number: B81B7/0067 , B81C1/00317 , B81B2203/0353 , B81C2201/0125 , B81C2201/0132 , B81C2201/0194
Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.
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公开(公告)号：US20190233280A1
公开(公告)日：2019-08-01
申请号：US16213019
申请日：2018-12-07
Applicant: Shenyang Silicon Technology Co., Ltd.
Inventor： Xiang LI
CPC classification number: B81C1/00047 , B08B3/08 , B32B37/06 , B32B38/0008 , B32B43/006 , B32B2038/0016 , B32B2310/14 , B32B2313/00 , B32B2457/14 , B81B1/004 , B81B2203/0315 , B81B2203/0353 , B81C1/00087 , B81C1/00357 , B81C1/00507 , B81C1/00849 , B81C2201/0116 , B81C2201/0125 , B81C2201/0178 , B81C2201/019 , B81C2201/0192 , B81C2201/0194
Abstract: A method for processing a silicon wafer with a through cavity structure. The method is operated in accordance with the following sequence: performing ion implantation on a silicon wafer or pattern wafer; implanting a dummy substrate; bonding the silicon wafer to the pattern wafer; performing grinding and polishing, and thinning the pattern wafer to a depth exposing the pattern; bonding; and peeling the dummy substrate. Compared with the prior art, the present invention is standard in operation, and the product quality can be effectively guaranteed. The product has high cost performance and excellent comprehensive technical effect. The present invention has expectable relatively large economic values and social values.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20180277388A1
公开(公告)日：2018-09-27
申请号：US15992223
申请日：2018-05-30
Applicant: Toshiba Memory Corporation
Inventor： Yukiteru MATSUI , Kyoichi SUGURO , Akifumi GAWASE , Takahiko KAWASAKI
IPC: H01L21/3115 , H01L21/3215 , H01L21/3105 , H01J37/317 , H01L21/321 , H01L21/306 , H01L21/304
CPC classification number: H01L21/31155 , B81C2201/0123 , B81C2201/0125 , H01J37/3171 , H01J2237/31711 , H01L21/304 , H01L21/30625 , H01L21/31053 , H01L21/32115 , H01L21/3212 , H01L21/3215
Abstract: A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.
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公开(公告)号：US20180201503A1
公开(公告)日：2018-07-19
申请号：US15923013
申请日：2018-03-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Michael T. Brigham , Christopher V. Jahnes , Cameron E. Luce , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , Eric J. White
CPC classification number: B81C1/0015 , B81B3/0021 , B81B2203/0118 , B81B2203/0315 , B81B2207/09 , B81C1/00047 , B81C1/00269 , B81C1/00365 , B81C1/00531 , B81C1/00936 , B81C2201/0104 , B81C2201/0107 , B81C2201/0121 , B81C2201/0125 , B81C2201/0132 , B81C2201/0176 , B81C2201/0181 , B81C2203/0109 , B81C2203/0145 , B81C2203/0714 , G06F17/5009
Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
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公开(公告)号：US20180201502A1
公开(公告)日：2018-07-19
申请号：US15916962
申请日：2018-03-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Michael T. Brigham , Christopher V. Jahnes , Cameron E. Luce , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , Eric J. White
CPC classification number: B81C1/0015 , B81B3/0021 , B81B2203/0118 , B81B2203/0315 , B81B2207/09 , B81C1/00047 , B81C1/00269 , B81C1/00365 , B81C1/00531 , B81C1/00936 , B81C2201/0104 , B81C2201/0107 , B81C2201/0121 , B81C2201/0125 , B81C2201/0132 , B81C2201/0176 , B81C2201/0181 , B81C2203/0109 , B81C2203/0145 , B81C2203/0714 , G06F17/5009
Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both metal material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
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公开(公告)号：US10008390B2
公开(公告)日：2018-06-26
申请号：US14643218
申请日：2015-03-10
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Yukiteru Matsui , Kyoichi Suguro , Akifumi Gawase , Takahiko Kawasaki
IPC: H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , H01L21/3115 , H01L21/321 , H01J37/317 , H01L21/304 , H01L21/306 , H01L21/3105 , H01L21/3215
CPC classification number: H01L21/31155 , B81C2201/0123 , B81C2201/0125 , H01J37/3171 , H01J2237/31711 , H01L21/304 , H01L21/30625 , H01L21/31053 , H01L21/32115 , H01L21/3212 , H01L21/3215
Abstract: A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.
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公开(公告)号：US09998843B2
公开(公告)日：2018-06-12
申请号：US15018625
申请日：2016-02-08
Inventor： Jung-Huei Peng , Chia-Hua Chu , Chun-wen Cheng , Chin-Yi Cho , Li-Min Hung , Yao-Te Huang
CPC classification number: H04R31/003 , B81C1/00158 , B81C2201/0125 , B81C2201/013 , B81C2201/053 , B81C2203/036 , H04R19/005 , H04R19/04 , H04R31/006 , H04R2201/003 , H04R2307/027
Abstract: The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.
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