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公开(公告)号:US06475369B1
公开(公告)日:2002-11-05
申请号:US09487408
申请日:2000-01-18
Applicant: Adam L. Cohen
Inventor: Adam L. Cohen
IPC: C25D502
CPC classification number: C25D5/10 , B33Y10/00 , B33Y70/00 , B81C1/00126 , B81C2201/0181 , B81C2201/0197 , B81C2201/032 , C25D1/00 , C25D1/003 , C25D5/022 , C25D5/12 , C25D5/22 , C25D17/06 , H01L21/2885 , H05K3/241 , Y10T428/12486 , Y10T428/239
Abstract: An electroplating method includes forming a layer, the forming of the layer includes: a) contacting a substrate with a first article, the first article includes a support and a conformable mask disposed in a pattern on the support; b) electroplating a first metal from a source of metal ions onto the substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the substrate. The method may further involve one or more of (1) selectively depositing or non-selectively depositing one or more additional materials to complete formation of the layer, (2) planarizing deposited material after each deposition or after all depositions for a layer, and/or (3) forming layers adjacent previously formed layers to build up a structure from a plurality of adhered layers. Electroplating articles and electroplating apparatus are also disclosed.
Abstract translation: 一种电镀方法包括形成层,所述层的形成包括:a)使基底与第一制品接触,所述第一制品包括以支持物的形式设置的支撑体和适形掩模; b)以第一图案将来自金属离子源的第一金属电镀到所述衬底上,所述第一图案对应于所述适形掩模图案的所述补体; 以及c)从所述基底中去除所述第一制品。 该方法还可以包括以下一个或多个:(1)选择性地沉积或非选择性地沉积一种或多种附加材料以完成层的形成,(2)在每次沉积之后或在所有沉积之后平坦化沉积的材料,以及/ 或(3)形成与先前形成的层相邻的层,以从多个附着层建立结构。 还公开了电镀制品和电镀装置。
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22.
公开(公告)号:US20240279051A1
公开(公告)日:2024-08-22
申请号:US18627028
申请日:2024-04-04
Applicant: HAMAMATSU PHOTONICS K.K.
Inventor: Daiki SUZUKI , Nao INOUE , Katsumi SHIBAYAMA
CPC classification number: B81B3/0072 , B81C1/00666 , G02B26/0833 , B81B2201/042 , B81B2207/07 , B81C2201/0104 , B81C2201/0181
Abstract: The damascene wiring structure includes a base including a main surface provided with a groove, an insulating layer including a first portion provided on an inner surface of the groove and a second portion provided on the main surface, a metal layer provided on the first portion, a wiring portion embedded in the groove, and a cap layer provided to cover the second portion and the wiring portion. A surface of a boundary part between the first portion and the second portion includes an inclined surface inclined with respect to a direction perpendicular to the main surface.
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公开(公告)号:US11926523B2
公开(公告)日:2024-03-12
申请号:US17470236
申请日:2021-09-09
Applicant: BEIJING VOYAGER TECHNOLOGY CO., LTD.
Inventor: Youmin Wang , Yue Lu
CPC classification number: B81C1/00174 , G02B26/0833 , G02B26/10 , B81C2201/0142 , B81C2201/0181 , B81C2203/032 , G01S7/4817
Abstract: Embodiments of the disclosure provide methods for microfabricating an omni-view peripheral scanning system. One exemplary method may include separately fabricating a reflector and a scanning MEMS mirror, and then bonding the microfabricated reflector with the scanning MEMS mirror to form the omni-view peripheral scanning system. The microfabricated reflector may include a cone-shaped bottom portion, and a via hole across the cone-shaped bottom portion. The microfabricated scanning MEMS mirror may include a MEMS actuation platform and a scanning mirror supported by the MEMS actuation platform. The scanning MEMS mirror may face the cone-shaped bottom portion of the reflector when forming the omni-view peripheral scanning system.
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公开(公告)号:US20230364604A1
公开(公告)日:2023-11-16
申请号:US18105936
申请日:2023-02-06
Applicant: PhysioLogic Devices, Inc.
Inventor: Peter C. Lord
CPC classification number: B01L3/502707 , F04B43/043 , B01L3/502715 , B81C3/001 , A61M5/14276 , B81C2201/0181 , A61M2205/0244 , B01L2400/0487
Abstract: In embodiments, a silicon part and a titanium part may be soldered together without breakage or instability. In embodiments, silicon and titanium may be soldered together with a soft solder joint including indium silver, where the temperature excursion between solder solidus and use temperature limits the strain between the two surfaces. In embodiments a silicon micropump surface may be treated to remove its silicon oxide coating, and then Ti—W, Nickel, and gold layers successively sputtered onto it. A corresponding titanium manifold may be ground flat, and plated with electroless nickel. The nickel plated manifold may then be baked, so as to create a transition from pure Ti to Ni—Ti alloy to pure Ni at the surface of the manifold, and for protection of the upper Ni surface, a layer of gold may be added. The two surfaces may then be soldered in forming gas.
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公开(公告)号:US20230294980A1
公开(公告)日:2023-09-21
申请号:US17697957
申请日:2022-03-18
CPC classification number: B81C1/00571 , B81B3/0021 , B81C2201/014 , B81C2201/0197 , B81C2201/0181 , B81C2201/0176 , B81C2201/0104 , B81B2201/0235 , B81B2201/0242 , B81B2203/0315
Abstract: A micro-electro-mechanical system (MEMS) device includes a supporting substrate, a cavity disposed in the supporting substrate, a stopper, and a MEMS structure. The stopper is disposed between the supporting substrate and the cavity, and an inner sidewall of the stopper is in contact with the cavity. The stopper includes a filling material surrounding a periphery of the cavity, and a liner wrapping around the filling material. The MEMS structure is disposed over the cavity and attached on the stopper and the supporting substrate.
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公开(公告)号:US11673797B2
公开(公告)日:2023-06-13
申请号:US17192126
申请日:2021-03-04
Inventor: Shinan Wang
CPC classification number: B81C1/00047 , B81B1/002 , G01L9/0042 , B81B2201/0264 , B81B2201/051 , B81B2203/0315 , B81C2201/0143 , B81C2201/0146 , B81C2201/0181
Abstract: A microstructure and a method for manufacturing the same includes: disposing a liquid film on a surface of a substrate, wherein a solid-liquid interface is formed where the liquid film is in contact with the substrate; and irradiating the substrate with a laser of a predetermined waveband to etch the substrate at the solid-liquid interface, wherein the position where the laser is irradiated on the solid-liquid interface moves at least along a direction parallel to the surface of the substrate, and the absorption rate of the liquid film for the laser is greater than the absorption rate of the substrate for the laser.
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公开(公告)号:US20180179052A1
公开(公告)日:2018-06-28
申请号:US15894119
申请日:2018-02-12
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Michael T. Brigham , Christopher V. Jahnes , Cameron E. Luce , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , Eric J. White
CPC classification number: B81C1/0015 , B81B3/0021 , B81B2203/0118 , B81B2203/0315 , B81B2207/09 , B81C1/00047 , B81C1/00269 , B81C1/00365 , B81C1/00531 , B81C1/00936 , B81C2201/0104 , B81C2201/0107 , B81C2201/0121 , B81C2201/0125 , B81C2201/0132 , B81C2201/0176 , B81C2201/0181 , B81C2203/0109 , B81C2203/0145 , B81C2203/0714 , G06F17/5009
Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
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28.
公开(公告)号:US09891189B2
公开(公告)日:2018-02-13
申请号:US15477982
申请日:2017-04-03
Applicant: International Business Machines Corporation
Inventor: Sebastian U. Engelmann , Stephen M. Rossnagel , Ying Zhang
IPC: G01N27/403 , G01N27/414 , B82B1/00 , B82B3/00 , G01N33/487
CPC classification number: G01N27/4146 , B01L3/502707 , B01L3/502761 , B01L2200/0663 , B01L2300/0861 , B01L2300/0887 , B01L2300/0896 , B81B2201/051 , B81C1/00119 , B81C2201/0181 , B82B1/005 , B82B3/008 , G01N27/4145 , G01N33/48721
Abstract: Techniques for fabricating horizontally aligned nanochannels are provided. In one aspect, a method of forming a device having nanochannels is provided. The method includes: providing a SOI wafer having a SOI layer on a buried insulator; forming at least one nanowire and pads in the SOI layer, wherein the nanowire is attached at opposite ends thereof to the pads, and wherein the nanowire is suspended over the buried insulator; forming a mask over the pads, the mask having a gap therein where the nanowire is exposed between the pads; forming an alternating series of metal layers and insulator layers alongside one another within the gap and surrounding the nanowire; and removing the nanowire to form at least one of the nanochannels in the alternating series of the metal layers and insulator layers. A device having nanochannels is also provided.
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29.
公开(公告)号:US20170370876A1
公开(公告)日:2017-12-28
申请号:US15477982
申请日:2017-04-03
Applicant: International Business Machines Corporation
Inventor: Sebastian U. Engelmann , Stephen M. Rossnagel , Ying Zhang
IPC: G01N27/414 , B82B1/00 , B82B3/00 , G01N33/487
CPC classification number: G01N27/4146 , B01L3/502707 , B01L3/502761 , B01L2200/0663 , B01L2300/0861 , B01L2300/0887 , B01L2300/0896 , B81B2201/051 , B81C1/00119 , B81C2201/0181 , B82B1/005 , B82B3/008 , G01N27/4145 , G01N33/48721
Abstract: Techniques for fabricating horizontally aligned nanochannels are provided. In one aspect, a method of forming a device having nanochannels is provided. The method includes: providing a SOI wafer having a SOI layer on a buried insulator; forming at least one nanowire and pads in the SOI layer, wherein the nanowire is attached at opposite ends thereof to the pads, and wherein the nanowire is suspended over the buried insulator; forming a mask over the pads, the mask having a gap therein where the nanowire is exposed between the pads; forming an alternating series of metal layers and insulator layers alongside one another within the gap and surrounding the nanowire; and removing the nanowire to form at least one of the nanochannels in the alternating series of the metal layers and insulator layers. A device having nanochannels is also provided.
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公开(公告)号:US20170272050A1
公开(公告)日:2017-09-21
申请号:US15610896
申请日:2017-06-01
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Keiichi Umeda , Hiroshi Yamada , Yasuhiro Aida
CPC classification number: H03H9/02102 , B81B3/0081 , B81C2201/0181 , H03H3/0072 , H03H3/0076 , H03H9/02259 , H03H9/17 , H03H9/171 , H03H9/2463 , H03H9/2489 , H03H2009/02496 , H03H2009/241
Abstract: A method for manufacturing a resonator that effectively addresses variations in resistivity for each wafer. The method for manufacturing a resonator includes forming a Si oxide film on a surface of a degenerated Si wafer, where the Si oxide film has a thickness set that is based on the doping amount of impurity in the degenerated Si wafer.
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