公开(公告)号：US09233372B2

公开(公告)日：2016-01-12

申请号：US14126116

申请日：2012-06-12

Applicant: Roland Guidat ,  Olivier Lobet ,  Paulo Gaspar Jorge Marques ,  Pierre Woehl

Inventor： Roland Guidat ,  Olivier Lobet ,  Paulo Gaspar Jorge Marques ,  Pierre Woehl

IPC: G01N15/06 ,  G01N33/00 ,  B01L3/00 ,  B01J19/00 ,  B81C99/00

CPC classification number: B01L3/527 ,  B01J19/0093 ,  B01J2219/00813 ,  B01J2219/00824 ,  B01J2219/00831 ,  B01J2219/00871 ,  B01J2219/00873 ,  B01J2219/00889 ,  B01L3/5027 ,  B01L3/502707 ,  B01L2200/025 ,  B01L2200/027 ,  B01L2200/028 ,  B01L2200/0689 ,  B01L2300/0867 ,  B01L2300/0874 ,  B01L2300/168 ,  B81B2201/058 ,  B81C99/0095 ,  B81C2201/019 ,  Y10T137/0318 ,  Y10T137/8359

Abstract: Embodiments of hybrid microfluidic assemblies comprise at least one microstructure that is formed of transparent material and is substantially free of non-transparent material and further comprise at least one microstructure that is formed of non-transparent material and is substantially free of transparent material.

Abstract translation: 混合微流体组件的实施例包括由透明材料形成并且基本上不含不透明材料的至少一个微结构，并且还包括由不透明材料形成并且基本上不含透明材料的至少一个微观结构。

公开(公告)号：US20150315015A1

公开(公告)日：2015-11-05

申请号：US14798213

申请日：2015-07-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

IPC: B81C1/00

CPC classification number: B81B7/0041 ,  B81C1/00158 ,  B81C1/00238 ,  B81C1/00301 ,  B81C2201/019 ,  B81C2203/00 ,  B81C2203/0714 ,  B81C2203/0792 ,  H01L23/10 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27831 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/32145 ,  H01L2224/83805 ,  H01L2224/8382 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A stacked semiconductor device includes a CMOS device and a MEMS device. The CMOS device includes a multilayer interconnect with metal elements disposed over the multilayer interconnect. The MEMS device includes metal sections with a first dielectric layer disposed over the metal sections. A cavity in the first dielectric layer exposes portions of the metal sections. A dielectric stop layer is disposed at least over the interior surface of the cavity. A movable structure is disposed over a front surface of the first dielectric layer and suspending over the cavity. The movable structure includes a second dielectric layer over the front surface of the first dielectric layer and suspending over the cavity, metal features over the second dielectric layer, and a flexible dielectric membrane over the metal features. The CMOS device is bonded to the MEMS device with the metal elements toward the flexible dielectric membrane.

Abstract translation: 叠层半导体器件包括CMOS器件和MEMS器件。 CMOS器件包括多层互连，金属元件设置在多层互连上。 MEMS器件包括具有设置在金属部分上方的第一介电层的金属部分。 第一电介质层中的空腔露出金属部分的部分。 电介质停止层至少设置在空腔的内表面上方。 可移动结构设置在第一介电层的前表面上并且悬挂在空腔上。 可移动结构包括在第一电介质层的前表面上并悬挂在空腔上的第二电介质层，在第二介电层上方的金属特征以及金属特征上的柔性介电膜。 CMOS器件通过金属元件接合到MEMS器件朝向柔性介电膜。

公开(公告)号：US09162879B2

公开(公告)日：2015-10-20

申请号：US14418986

申请日：2012-08-01

Applicant: Mitsuru Koarai

Inventor： Mitsuru Koarai

IPC: H01L29/40 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00269 ,  B81B7/008 ,  B81C1/00238 ,  B81C2201/019 ,  B81C2203/0109 ,  B81C2203/035 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device is obtained in such a way that a MEMS substrate having a MEMS element mounted thereon and a CMOS substrate are bonded together at bonding surfaces and with a bonding material M having fluidity, wherein the MEMS substrate has a bonding projection part provided to project from a substrate main body and having the bonding surface and a gap formation part disposed between the bonding projection part and the MEMS element, and the gap formation part is supported by the bonding projection part via a plurality of support pieces extending from the bonding projection part and forms reception gaps, which are capable of receiving the bonding material M extruded from the bonding surface to the side of the MEMS element, between the wall surface thereof and the bonding projection part.

Abstract translation: 获得电子器件，使得其上安装有MEMS元件的MEMS衬底和CMOS衬底在接合表面处接合在一起并且具有流动性的接合材料M，其中MEMS衬底具有设置成投影的接合突出部分 并且具有接合面和设置在接合突起部与MEMS元件之间的间隙形成部，并且间隙形成部通过从接合突出部延伸的多个支撑部被接合突起部支撑， 并且形成接收间隙，其能够接收在其壁表面和接合突出部分之间从接合表面到MEMS元件的一侧挤出的接合材料M.

公开(公告)号：US09150412B2

公开(公告)日：2015-10-06

申请号：US14449317

申请日：2014-08-01

Applicant: KROHNE Messtechnik GmbH

Inventor： Winfred Kuipers

IPC: B81C3/00 ,  B81B7/02 ,  B81C1/00 ,  G01N27/62 ,  G01N30/68 ,  G01N30/60 ,  G01N30/88

CPC classification number: B81C3/001 ,  B81B7/02 ,  B81B2201/0292 ,  B81C1/00341 ,  B81C2201/019 ,  G01N27/626 ,  G01N30/6095 ,  G01N30/68 ,  G01N2030/8881

Abstract: A method for producing a functional unit with a gas converter (1) and a flame ionization detector (10) is produced with the gas converter (1) and the flame ionization detector (10) being connected together as parts of a multi-layer ceramic (6).

Abstract translation: 制造具有气体转换器（1）和火焰离子化检测器（10）的功能单元的方法，其中气体转换器（1）和火焰离子化检测器（10）作为多层陶瓷的部件连接在一起 （6）。

公开(公告)号：US20150279664A1

公开(公告)日：2015-10-01

申请号：US14670875

申请日：2015-03-27

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Hung-Lin Yin

IPC: H01L21/02 ,  H01L21/461 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/02255 ,  B81C1/00047 ,  B81C2201/019 ,  H01L21/02554 ,  H01L21/187 ,  H01L21/461 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L24/92 ,  H01L2224/0355 ,  H01L2224/05551 ,  H01L2224/05638 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/80006 ,  H01L2224/80013 ,  H01L2224/80894 ,  H01L2224/80896 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01014 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2221/68381 ,  H01L21/306 ,  H01L2224/03

Abstract: The present disclosure provides a method for fabricating semiconductor devices having high-precision gaps. The method includes steps of providing a first wafer; forming two or more regions having various ion dosage concentrations on a first surface of the first wafer; thermally oxidizing the first wafer so as to grow oxide layers with various thicknesses on the first surface of the first wafer; and bonding a second wafer to the thickest oxide layer of the first wafer so as to form one or more gaps.

Abstract translation: 本公开提供了一种制造具有高精度间隙的半导体器件的方法。 该方法包括提供第一晶片的步骤; 在所述第一晶片的第一表面上形成具有各种离子剂量浓度的两个或更多个区域; 热氧化第一晶片以在第一晶片的第一表面上生长具有各种厚度的氧化物层; 以及将第二晶片接合到所述第一晶片的最厚氧化物层，以形成一个或多个间隙。

公开(公告)号：US09120298B2

公开(公告)日：2015-09-01

申请号：US14028106

申请日：2013-09-16

Applicant: Tej Patel ,  Ryan Revilla ,  Matthew D'Ooge

Inventor： Tej Patel ,  Ryan Revilla ,  Matthew D'Ooge

IPC: B32B37/00 ,  B32B37/02 ,  B32B37/14 ,  B32B37/18 ,  B01L3/00 ,  B81C3/00 ,  B32B37/12 ,  B81B1/00 ,  G01N27/447 ,  G01N35/00

CPC classification number: B32B37/1284 ,  B01J2219/00783 ,  B01L3/502707 ,  B01L2200/02 ,  B01L2300/0816 ,  B01L2300/0887 ,  B01L2300/12 ,  B01L2300/16 ,  B32B37/02 ,  B32B2037/1253 ,  B32B2307/518 ,  B32B2310/0831 ,  B32B2310/0843 ,  B32B2315/08 ,  B32B2367/00 ,  B81B2201/058 ,  B81C1/00119 ,  B81C3/001 ,  B81C2201/019 ,  G01N27/44791 ,  G01N2035/00158

Abstract: A microfluidic chip includes a thin biaxially-oriented polyethylene terephthalate (“BoPET”) film and a micro-channel in the BoPET film. A method for manufacturing a microfluidic chip includes coating UV epoxy on a first side of a BoPET film, placing the BoPET film on a first substrate with the first side facing the first substrate, curing the UV epoxy on the first side of the BoPET film to attach the BoPET film on the first substrate; forming at least one microfluidic pathway in the BoPET film, coating UV epoxy on a first side of a second substrate, placing the second substrate on the BoPET film with the first side of the second substrate facing a second side of the BoPET film, and curing the UV epoxy on the first side of the second substrate to attach the BoPET film to the second substrate. The microfluidic chip may be a multi-layered chip.

Abstract translation: 微流控芯片包括薄双轴取向的聚对苯二甲酸乙二醇酯（“BoPET”）薄膜和BoPET薄膜中的微通道。 微流控芯片的制造方法包括在BoPET膜的第一面上涂布UV环氧树脂，将该BoPET膜放置在第一衬底上，其第一面朝向第一衬底，使BoPET膜的第一侧的UV环氧树脂固化 将BoPET膜附着在第一衬底上; 在所述BoPET膜中形成至少一个微流体通路，在第二基底的第一侧上涂覆UV环氧树脂，将所述第二基底放置在所述BoPET膜上，其中所述第二基底的第一面朝向所述BoPET膜的第二侧， 在第二衬底的第一侧上的UV环氧树脂将BoPET膜附接到第二衬底。 微流控芯片可以是多层芯片。

公开(公告)号：US20150210541A1

公开(公告)日：2015-07-30

申请号：US14504953

申请日：2014-10-02

Applicant: Yu-Fu Kang ,  Chiung-Cheng Lo

Inventor： Yu-Fu Kang ,  Chiung-Cheng Lo

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00285 ,  B81B7/0038 ,  B81B7/02 ,  B81B2207/015 ,  B81C2201/013 ,  B81C2201/019 ,  B81C2203/0792

Abstract: A MEMS chip includes a cap layer and a composite device layer. The cap layer includes a substrate. The substrate has a first region and a second region, wherein the first region includes plural first trenches and the second region has plural second trenches. The first region has a first etch pattern density and the second region has a second etch pattern density, wherein the first etch pattern density is higher than the second etch pattern density to form chambers of different pressures.

Abstract translation: MEMS芯片包括盖层和复合器件层。 盖层包括基底。 衬底具有第一区域和第二区域，其中第一区域包括多个第一沟槽，而第二区域具有多个第二沟槽。 第一区域具有第一蚀刻图案密度，第二区域具有第二蚀刻图案密度，其中第一蚀刻图案密度高于第二蚀刻图案密度以形成不同压力的室。

公开(公告)号：US09079761B2

公开(公告)日：2015-07-14

申请号：US13906080

申请日：2013-05-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

IPC: B81C3/00 ,  B81B7/00 ,  H01L25/00 ,  H01L23/10 ,  H01L23/00

CPC classification number: B81B7/0041 ,  B81C1/00158 ,  B81C1/00238 ,  B81C1/00301 ,  B81C2201/019 ,  B81C2203/00 ,  B81C2203/0714 ,  B81C2203/0792 ,  H01L23/10 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27831 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/32145 ,  H01L2224/83805 ,  H01L2224/8382 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A stacked semiconductor device includes a CMOS device and a MEMS device. The CMOS device includes a multilayer interconnect with metal elements disposed over the multilayer interconnect. The MEMS device includes metal sections with a first dielectric layer disposed over the metal sections. A cavity in the first dielectric layer exposes portions of the metal sections. A dielectric stop layer is disposed at least over the interior surface of the cavity. A movable structure is disposed over a front surface of the first dielectric layer and suspending over the cavity. The movable structure includes a second dielectric layer over the front surface of the first dielectric layer and suspending over the cavity, metal features over the second dielectric layer, and a flexible dielectric membrane over the metal features. The CMOS device is bonded to the MEMS device with the metal elements toward the flexible dielectric membrane.

Abstract translation: 叠层半导体器件包括CMOS器件和MEMS器件。 CMOS器件包括多层互连，金属元件设置在多层互连上。 MEMS器件包括具有设置在金属部分上方的第一介电层的金属部分。 第一电介质层中的空腔露出金属部分的部分。 电介质停止层至少设置在空腔的内表面上方。 可移动结构设置在第一介电层的前表面上并且悬挂在空腔上。 可移动结构包括在第一电介质层的前表面上并悬挂在空腔上的第二电介质层，在第二介电层上方的金属特征以及金属特征上的柔性介电膜。 CMOS器件通过金属元件接合到MEMS器件朝向柔性介电膜。

公开(公告)号：US09067779B1

公开(公告)日：2015-06-30

申请号：US14635197

申请日：2015-03-02

Applicant: Butterfly Network, Inc.

Inventor： Jonathan M. Rothberg ,  Susan A. Alie ,  Keith G. Fife ,  Nevada J. Sanchez ,  Tyler S. Ralston

IPC: H01L29/00 ,  B81C1/00

CPC classification number: G01N29/2406 ,  A61B8/4483 ,  B06B1/0292 ,  B81B7/007 ,  B81B2201/0271 ,  B81C1/00238 ,  B81C1/00301 ,  B81C2201/019 ,  B81C2203/036 ,  B81C2203/0792 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/146 ,  H01L2924/1461

Abstract: Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

Abstract translation: 与互补金属氧化物半导体（CMOS）基板集成的微加工超声换能器以及制造这种装置的方法进行了描述。 制造可能涉及两个单独的晶片结合步骤。 可以使用晶片结合来制造衬底中的密封空腔。 晶片接合也可用于将衬底粘合到另一衬底，例如CMOS晶片。 至少第二晶片接合可以在低温下进行。

公开(公告)号：US09027239B2

公开(公告)日：2015-05-12

申请号：US13511486

申请日：2010-12-17

Applicant: Andreas Fischer ,  Göran Stemme ,  Frank Niklaus ,  Niklas Roxhed

Inventor： Andreas Fischer ,  Göran Stemme ,  Frank Niklaus ,  Niklas Roxhed

IPC: H01R9/00 ,  H05K3/00 ,  B81C1/00 ,  B01L3/00

CPC classification number: B81C1/00293 ,  B01L3/502707 ,  B01L2300/042 ,  B81B2201/058 ,  B81B2203/0315 ,  B81C2201/019 ,  B81C2203/0145 ,  Y10T29/49117 ,  Y10T29/49151 ,  Y10T29/49153 ,  Y10T29/49826 ,  Y10T29/49885

Abstract: A method for at least partially inserting a plug into a hole, said method comprising the steps of a) providing a at least one substrate with at least one hole wherein said at least one hole has a largest dimension of from 1 μm to 300 μm, b) providing a piece of material, wherein said piece of material has a larger dimension than said at least one hole, c) pressing said piece of material against the hole with a tool so that a plug is formed, wherein at least a part of said piece of material is pressed into said hole, d) removing the tool from the piece of material. There is further disclosed a plugged hole manufactured with the method. One advantage of an embodiment is that an industrially available wire bonding technology can be used to seal various cavities. The existing wire bonding technology makes the plugging fast and cheap.

Abstract translation: 一种用于至少部分地将插头插入孔中的方法，所述方法包括以下步骤：a）提供具有至少一个孔的至少一个基底，其中所述至少一个孔具有1μm至300μm的最大尺寸， b）提供一块材料，其中所述材料片具有比所述至少一个孔更大的尺寸，c）用工具将所述材料件压靠在孔上，从而形成插塞，其中至少部分 所述材料被压入所述孔中，d）从所述材料上移除所述工具。 还公开了一种使用该方法制造的堵塞孔。 一个实施例的一个优点是可以使用工业上可用的引线接合技术来密封各种空腔。 现有的导线接合技术使堵塞快速便宜。