公开(公告)号：US09019035B2

公开(公告)日：2015-04-28

申请号：US12674221

申请日：2008-07-24

Applicant: Risato Ohhira

Inventor： Risato Ohhira

IPC: H01P3/08 ,  H05K1/02 ,  H01P1/04 ,  H01L23/66

CPC classification number: H05K1/0219 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/15323 ,  H01L2924/16195 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01P1/047 ,  H01P3/08 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09363 ,  H05K2201/09618 ,  H05K2201/09663 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The high-frequency wiring board of the present invention includes: first coplanar lines provided with a first signal line and a first planar ground pattern formed on the same wiring layer as the first signal line; second coplanar lines provided with a second signal line formed on a different wiring layer than the first signal line and a second planar ground pattern formed on the same wiring layer as the second signal line; and a first ground pattern formed on the same wiring layer as the first coplanar lines. The first coplanar lines and the second coplanar lines are connected. At least the first ground pattern and the first planar ground pattern are separated in a region following the second signal line from the connection of the first signal line and the second signal line.

Abstract translation: 本发明的高频布线基板包括：第一共面线，设置有与第一信号线在同一布线层上形成的第一信号线和第一平面接地图案; 第二共面线设置有形成在与第一信号线不同的布线层上的第二信号线和形成在与第二信号线相同的布线层上的第二平面接地图案; 以及形成在与第一共面线相同的布线层上的第一接地图案​​。 第一共面线和第二共面线被连接。 至少第一接地图案​​和第一平面接地图案在第二信号线之后的区域中与第一信号线和第二信号线的连接分开。

公开(公告)号：US20150041859A1

公开(公告)日：2015-02-12

申请号：US13962622

申请日：2013-08-08

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer

IPC: H01L23/522 ,  H01L29/778

CPC classification number: H01L23/5226 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/48091 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/0761 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09972 ,  H01L2924/00014

Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.

Abstract translation: 再分配板包括：第一导电层，包括用于低电压信号的再分配结构;第二导电层，包括用于高电压信号的再分配结构;以及非导电层。 第二导电层通过非导电层与第一导电层间隔开。 再分配板还包括从再分布板的安装表面延伸到第二导电层的导电连接器。 导电连接器被第一导电层的低电压迹线围绕。

公开(公告)号：US20150016069A1

公开(公告)日：2015-01-15

申请号：US14004443

申请日：2013-07-15

Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.

Inventor： Jianyong Fu ,  Anle Hu ,  Xiaoping Tan

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K3/328 ,  H05K2201/09136 ,  H05K2201/093 ,  H05K2201/0969

Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a main body. A first surface of the main body is a connecting surface for electrical components. A second surface of the main body is a conductive cooper foil layer operating as ground wires. A plurality of grooves is arranged on the conductive cooper foil layer. The grooves pass through the conductive cooper foil layer to connect to the main body of the PCB. The thermal stress generated in the PCB welding process can be effectively released via the grooves. The inflation of the conductive cooper coil is relieved such that the PCB is prevented from being wrapped or cooper bubbling. In this way, the operation efficiency is enhanced and the manufacturing cost is reduced.

Abstract translation: 公开了印刷电路板（PCB）。 PCB包括主体。 主体的第一表面是用于电气部件的连接表面。 主体的第二表面是作为接地线操作的导电铜箔层。 多个凹槽布置在导电铜箔层上。 槽通过导电铜箔层连接到PCB的主体。 PCB焊接过程中产生的热应力可以通过槽有效释放。 释放导电铜线圈的膨胀，使得防止PCB被包裹或起泡。 这样，提高了运行效率，降低了制造成本。

公开(公告)号：US08885357B2

公开(公告)日：2014-11-11

申请号：US13345247

申请日：2012-01-06

Applicant: Hyunjun Kim ,  Jeffrey S. Conger ,  Gregory E. Scott

Inventor： Hyunjun Kim ,  Jeffrey S. Conger ,  Gregory E. Scott

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0225 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/114 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09609 ,  H05K2201/09618 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multi-layer printed circuit board has a number of landing pads that are configured to engage a connector secured thereto. Between the landing pads associated with different signals is at least one micro via that is electrically connected to a ground plane on an outer surface of the multi-layer printed circuit board, and a ground plane on an inner layer of the multi-layer printed circuit board.

Abstract translation: 多层印刷电路板具有多个着陆焊盘，其被配置为接合固定到其上的连接器。 在与不同信号相关联的着陆垫之间是至少一个微通孔，其电连接到多层印刷电路板的外表面上的接地平面，以及多层印刷电路的内层上的接地平面 板。

公开(公告)号：US20130128647A1

公开(公告)日：2013-05-23

申请号：US13748167

申请日：2013-01-23

Applicant: Renesas Technology Corporation

Inventor： Takafumi BETSUI ,  Naoto TAOKA ,  Motoo SUWA ,  Shigezumi MATSUI ,  Norihiko SUGITA ,  Yoshiharu FUKUSHIMA

IPC: G11C5/06

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US08386992B2

公开(公告)日：2013-02-26

申请号：US13310217

申请日：2011-12-02

Applicant: Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract translation: 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US08319424B2

公开(公告)日：2012-11-27

申请号：US13284031

申请日：2011-10-28

Applicant: Shunpei Yamazaki ,  Takeshi Fukunaga

Inventor： Shunpei Yamazaki ,  Takeshi Fukunaga

IPC: H05B33/06 ,  H01J1/62 ,  H01L33/00

CPC classification number: H01L51/524 ,  G01N33/497 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/3227 ,  H01L27/3262 ,  H01L27/3276 ,  H01L27/3279 ,  H01L27/3288 ,  H01L27/329 ,  H01L31/153 ,  H01L33/62 ,  H01L51/0097 ,  H01L51/5203 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/5315 ,  H01L2251/5338 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/093 ,  H05K2201/10128 ,  H05K2201/1031 ,  Y02P70/611 ,  H01L2924/00

Abstract: A light-emitting device having the quality of an image high in homogeneity is provided. A printed wiring board (second substrate) (107) is provided facing a substrate (first substrate) (101) that has a luminous element (102) formed thereon. A PWB side wiring (second group of wirings) (110) on the printed wiring board (107) is electrically connected to element side wirings (first group of wirings) (103, 104) by anisotropic conductive films (105a, 105b). At this point, because a low resistant copper foil is used to form the PWB side wiring (110), a voltage drop of the element side wirings (103, 104) and a delay of a signal can be reduced. Accordingly, the homogeneity of the quality of an image is improved, and the operating speed of a driver circuit portion is enhanced.

Abstract translation: 提供具有均匀性高的图像质量的发光装置。 面向其上形成有发光元件（102）的基板（第一基板）（101）设置有印刷布线板（第二基板）（107）。 印刷电路板（107）上的PWB侧布线（第二组布线）（110）通过各向异性导电膜（105a，105b）与元件侧布线（第一组布线）（103,104）电连接。 此时，由于使用低电阻铜箔来形成PWB侧布线（110），可以降低元件侧布线（103,104）的电压降和信号的延迟。 因此，提高了图像质量的均匀性，并且提高了驱动器电路部分的操作速度。

公开(公告)号：US20120132461A1

公开(公告)日：2012-05-31

申请号：US12981477

申请日：2010-12-30

Applicant: TSUNG-SHENG HUANG

Inventor： TSUNG-SHENG HUANG

IPC: H05K1/16

CPC classification number: H05K1/0265 ,  H05K1/0201 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0979

Abstract: A printed circuit board includes a top layer and a bottom layer. A power supply and an electronic component are located on the top layer. The power supply is connected to the top layer and the bottom layer through a first via. A number of second vias extend through the printed circuit board and are connected to the top layer and the bottom layer. The distance between each second via and the electronic component is the same.

Abstract translation: 印刷电路板包括顶层和底层。 电源和电子元件位于顶层。 电源通过第一通孔连接到顶层和底层。 多个第二通孔延伸穿过印刷电路板并连接到顶层和底层。 每个第二通孔和电子部件之间的距离是相同的。

公开(公告)号：US08143528B2

公开(公告)日：2012-03-27

申请号：US12277250

申请日：2008-11-24

Applicant: Hou-Yuan Chou

Inventor： Hou-Yuan Chou

IPC: H05K1/03

CPC classification number: H05K1/0268 ,  G01R31/2818 ,  H05K1/0237 ,  H05K1/11 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2203/162 ,  Y10T29/49124 ,  Y10T29/49147

Abstract: A printed circuit board includes a signal layer, an insulation layer, and a reference layer. A transmission line is located on the signal layer. A probing pad is located on the transmission line. Two aligned slots defined in opposite sides of the reference layer leaving a connecting portion. The slots and the connecting portion are in vertical alignment with the probing pad. The signal layer, the insulation layer, and the reference layer are configured in a cascading order. An arrangement of the signal layer in relation to the reference layer including the slots and the connecting portion reduces a capacitance effect caused by the probing pad.

Abstract translation: 印刷电路板包括信号层，绝缘层和参考层。 传输线位于信号层上。 探测板位于传输线上。 限定在参考层的相对侧中的两个对准的槽留下连接部分。 槽和连接部分与探测板垂直对准。 信号层，绝缘层和参考层以级联顺序配置。 信号层相对于包括狭缝和连接部分的参考层的布置减小了由探测垫引起的电容效应。

公开(公告)号：US07969261B2

公开(公告)日：2011-06-28

申请号：US12392504

申请日：2009-02-25

Applicant: Norio Okada

Inventor： Norio Okada

IPC: H01P3/08

CPC classification number: H01P3/081 ,  H05K1/0219 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0239 ,  H05K1/025 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663

Abstract: A transmission line substrate includes: a dielectric substrate; a signal line disposed on the upper surface of the dielectric substrate; first and second ground conductors disposed on the upper surface of the dielectric substrate, field-coupled to the signal line, having potentials different from each other; a dielectric film disposed between an overlapping part of the first ground conductor and a part of the second ground conductor at which the first and second ground conductors overlap each other, to constitute a MIM capacitor; a capacitor connected between the first ground conductor and the second ground conductor in parallel with the dielectric film; and a resistor connected between the first ground conductor and the second ground conductor in series with the capacitor.

Abstract translation: 传输线基板包括：电介质基板; 设置在电介质基板的上表面上的信号线; 第一和第二接地导体，其设置在电介质基板的上表面上，场耦合到信号线，具有彼此不同的电位; 电介质膜，设置在所述第一接地导体的重叠部分与所述第二接地导体的所述第一接地导体和所述第二接地导体彼此重叠的部分之间，以构成MIM电容器; 电容器，其与所述电介质膜平行地连接在所述第一接地导体和所述第二接地导体之间; 以及连接在与电容器串联的第一接地导体和第二接地导体之间的电阻器。