公开(公告)号：US20070119541A1

公开(公告)日：2007-05-31

申请号：US11603884

申请日：2006-11-22

Applicant: Kenichi Kawabata ,  Takaaki Morita

Inventor： Kenichi Kawabata ,  Takaaki Morita

IPC: B32B3/00

CPC classification number: H05K3/4652 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/0044 ,  H05K3/0058 ,  H05K3/4602 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/0358 ,  H05K2201/09518 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/1105 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49128 ,  Y10T428/24917 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A multilayer circuit board comprises core layers 101 and 102 made of a core material impregnated with resin, resin layers 111 and 112 interposed between the core layers 101 and 102, a wiring pattern 140 embedded in the resin layers 111 and 112. The core layers 101 and 102 have a thickness of 100 μm or smaller, whereby the entire board can significantly be thinned. Furthermore, the less strong resin layers 111 and 112 are interposed between the hard core layers 101 and 102, whereby the entire board has increased strength.

Abstract translation: 多层电路板包括由浸渍有树脂的芯材制成的芯层101和102，插入在芯层101和102之间的树脂层111和112，嵌入在树脂层111和112中的布线图案140。 芯层101和102的厚度为100μm或更小，由此整个板可以显着地变薄。 此外，较不强的树脂层111和112插入在硬芯层101和102之间，由此整个板具有增加的强度。

公开(公告)号：US07217370B2

公开(公告)日：2007-05-15

申请号：US11073615

申请日：2005-03-08

Applicant: Hiroshi Sugimoto ,  Tatsuya Ohtaka ,  Shigeharu Takahagi

Inventor： Hiroshi Sugimoto ,  Tatsuya Ohtaka ,  Shigeharu Takahagi

IPC: H01B13/00

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09527 ,  H01L2224/05599

Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.

Abstract translation: 具有微带结构的布线板具有：第一导体层，其在其外部端子（接合焊盘）中设置有与半导体芯片连接的导体布线; 第二导体层，其设置有通过通孔连接到接地布线的导体图案，用于向半导体芯片提供接地电位; 以及第三导体层，其具有通过通孔连接到电源布线的电源端子，用于向半导体芯片提供除了地电位以外的电位的操作电源，通过通孔连接到 用于发送电信号的信号线路，以及通过通孔连接到第二导体层中的导体图案的接地端子。

公开(公告)号：US20070099449A1

公开(公告)日：2007-05-03

申请号：US11589332

申请日：2006-10-30

Applicant: Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

Inventor： Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

IPC: H01R12/00

CPC classification number: H01L24/11 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/81121 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0269 ,  H05K1/112 ,  H05K1/186 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10674 ,  H05K2203/166

Abstract: According to one embodiment, a printed circuit board includes a first dielectric layer, a circuit component mounted on the first dielectric layer, and a second dielectric layer. The first dielectric layer is provided with a via hole which opens at a surface thereof and in which a conductive layer is provided, and a conductive pattern connected electrically to the conductive layer of the via hole. The circuit component is provided with a bump at least a part of which is inserted in the via hole and bonded to an inner surface of the via hole. The second dielectric layer is formed provided with another conductive pattern and laminated to the first dielectric layer to cover the circuit component.

Abstract translation: 根据一个实施例，印刷电路板包括第一电介质层，安装在第一电介质层上的电路部件和第二电介质层。 第一介电层设置有在其表面开口并且其中设置有导电层的通孔以及与通孔的导电层电连接的导电图案。 电路部件设置有凸块，其中至少一部分插入通孔中并结合到通孔的内表面。 第二电介质层被形成为设置有另一个导电图案并层压到第一电介质层以覆盖电路部件。

公开(公告)号：US20060273816A1

公开(公告)日：2006-12-07

申请号：US11407485

申请日：2006-04-19

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: G01R31/26

CPC classification number: G01R1/0483 ,  H05K1/113 ,  H05K3/20 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09527 ,  H05K2201/09563

Abstract: A circuit board having a reverse build-up structure includes a supporting carrier formed with a through cavity; a dielectric layer having a first surface and a second surface opposite to the first surface and being extended into the through cavity, one end of the through cavity being sealed by the first surface; a plurality of electrically contact pads embedded in the dielectric layer and appeared on the first surface of the dielectric layer and corresponding to the through cavity of the supporting carrier; and a circuit layer formed on the second layer of the dielectric layer and electrically connected to the electrically contact pads through a plurality of conductive vias embedded in the dielectric layer.

Abstract translation: 具有反向积聚结构的电路板包括形成有通孔的支撑载体; 电介质层，其具有第一表面和与所述第一表面相对的第二表面并且延伸到所述通孔中，所述通孔的一端由所述第一表面密封; 多个电接触焊盘，其嵌入所述电介质层中并且出现在所述电介质层的所述第一表面上并对应于所述支撑载体的通孔; 以及形成在所述介电层的所述第二层上并通过嵌入在所述电介质层中的多个导电通孔电连接到所述电接触焊盘的电路层。

公开(公告)号：US20060145345A1

公开(公告)日：2006-07-06

申请号：US11086625

申请日：2005-03-22

Applicant: Jae Choi ,  Young Shin

Inventor： Jae Choi ,  Young Shin

IPC: H01L23/34

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19043 ,  H05K1/113 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same.

Abstract translation: 公开了一种球栅阵列（BGA）封装基板，其中引线接合焊盘和焊球焊盘形成在通孔上，使电路图案的设计和高密度电路图案具有高自由度，以及方法 的制造。

公开(公告)号：US07049526B2

公开(公告)日：2006-05-23

申请号：US10700209

申请日：2003-11-03

Applicant: Christopher C. Jones

Inventor： Christopher C. Jones

IPC: H05K1/00

CPC classification number: H05K3/421 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/243 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49165

Abstract: A system may include a first microvia pad, a second microvia pad having a projection extending in a direction toward the first microvia pad, and a microvia electrically coupled to the first microvia pad and to the second microvia pad.

公开(公告)号：US07046501B2

公开(公告)日：2006-05-16

申请号：US11100827

申请日：2005-04-06

Applicant: Yoshiomi Tsuji

Inventor： Yoshiomi Tsuji

IPC: H01G4/228 ,  H01G4/30 ,  H01G4/05

CPC classification number: H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09718

Abstract: A capacitor-embedded substrate for reliably compensating for fluctuation of a power source voltage is provided. A decoupling capacitor is formed between an input side electrode layer and an output side electrode layer via interlayer insulating layers, the decoupling capacitor includes a ground layer, a power source layer, and a dielectric layer interposed therebetween. A plurality of power supply terminals used for power supply to a semiconductor device is formed by patterning the output side electrode layer and is connected to the power source layer via a capacitor via.

Abstract translation: 提供了用于可靠地补偿电源电压波动的电容器嵌入式基板。 在输入侧电极层和输出侧电极层之间经由层间绝缘层形成去耦电容器，去耦电容器包括接地层，电源层和介于其间的电介质层。 用于向半导体器件供电的多个电源端子通过对输出侧电极层进行构图而形成，并通过电容器通孔连接到电源层。

公开(公告)号：US06986917B2

公开(公告)日：2006-01-17

申请号：US10408588

申请日：2003-04-07

Applicant: Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: B05D3/04

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

Abstract translation: 在具有导体电路（6）的绝缘板（7）的表面上印刷包括热固性树脂的阻焊剂。 然后将阻焊剂热固化以形成具有低热膨胀系数的绝缘膜（1）。 然后将激光束（2）施加到要形成开口的绝缘膜的部分，以烧掉用于形成开口（10）的相同部分，由此导体电路（6）暴露。 该开口可以通过在其内表面上形成金属电镀膜而形成为导电孔。 优选地，形成外部连接垫以覆盖开口。 通过使用在电镀完成后优选用激光束切断的电镀铅来形成金属涂膜。

公开(公告)号：US20050092521A1

公开(公告)日：2005-05-05

申请号：US10700209

申请日：2003-11-03

Applicant: Christopher Jones

Inventor： Christopher Jones

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/421 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/243 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49165

Abstract: A system may include a first microvia pad, a second microvia pad having a projection extending in a direction toward the first microvia pad, and a microvia electrically coupled to the first microvia pad and to the second microvia pad.

Abstract translation: 系统可以包括第一微孔垫，具有沿朝向第一微孔垫的方向延伸的突起的第二微孔垫，以及电耦合到第一微孔垫和第二微孔垫的微孔。

公开(公告)号：US06884945B2

公开(公告)日：2005-04-26

申请号：US10384658

申请日：2003-03-11

Applicant: Dock-Heung Kim ,  Yong-Il Kim

Inventor： Dock-Heung Kim ,  Yong-Il Kim

IPC: H05K3/46 ,  H01L23/12 ,  H05K1/11 ,  H05K3/00 ,  H05K3/28 ,  H01R12/04

CPC classification number: H05K3/4652 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/0097 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913

Abstract: A multi-layer printed circuit board on which insulation resin layers and circuit pattern layers are alternatively stacked to form multiple layers, including: an insulation resin layer; a circuit pattern formed at the upper surface of the insulation resin layer; a blind via hole formed penetrating the insulation resin layer and the circuit pattern; a plated layer formed at the upper surface of the circuit pattern, at the inner wall face and the bottom of the blind via hole; an inner lead bump pad formed at the surface of the plated layer which is exposed to the lower surface of the insulation resin layer; and an outer lead bump pad formed on the circuit pattern which is formed at the upper surface of the insulation resin layer, whereby the problem of defective attachment of a bump due to a void present in a blind via hole is eliminated.

Abstract translation: 一种多层印刷电路板，其上绝缘树脂层和电路图案层交替堆叠形成多层，包括：绝缘树脂层; 形成在所述绝缘树脂层的上表面的电路图案; 穿过绝缘树脂层和电路图案的盲通孔; 在电路图案的上表面形成在盲通孔的内壁面和底部的镀层; 内部引线凸块焊盘，其形成在所述绝缘树脂层的下表面的所述镀层的表面， 以及形成在电路图案上的外部引线凸块焊盘，其形成在绝缘树脂层的上表面处，由此消除了由于存在于盲孔中的空隙而引起的凸起不良的附着问题。