公开(公告)号：US20090205852A1

公开(公告)日：2009-08-20

申请号：US12193460

申请日：2008-08-18

Applicant: Chun-Chien Chen ,  Tsung-Yuan Chen

Inventor： Chun-Chien Chen ,  Tsung-Yuan Chen

IPC: H05K1/00 ,  H05K3/02

CPC classification number: H05K3/44 ,  H05K3/20 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/445 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2203/0369 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24273 ,  Y10T428/24917

Abstract: A manufacturing method of a circuit board is provided. A metal core is provided. A conductive layer is formed on each of some carriers. The carriers and dielectric layers are laminated at both sides of the metal core to form a stacked structure. Each of the dielectric layers is located between the corresponding carrier and the metal core, and a portion of the conductive layer is embedded in the corresponding dielectric layer. Then, the carriers are removed. A blind via and/or a through via are/is formed in the stacked structure to connect the corresponding conductive layer and the metal core and/or connect the conductive layers at both sides of the metal core, wherein the through via penetrates the metal core. The conductive layer on a surface of the dielectric layer is removed.

Abstract translation: 提供电路板的制造方法。 提供金属芯。 在一些载体的每一个上形成导电层。 载体和电介质层被层叠在金属芯的两侧以形成堆叠结构。 每个电介质层位于相应的载体和金属芯之间，并且导电层的一部分嵌入相应的介电层中。 然后，移除载体。 在堆叠结构中形成盲通孔和/或通孔，以将相应的导电层和金属芯连接和/或连接金属芯两侧的导电层，其中通孔穿过金属芯 。 去除介电层表面上的导电层。

公开(公告)号：US20090039498A1

公开(公告)日：2009-02-12

申请号：US11834395

申请日：2007-08-06

Applicant: Reinhold Bayerer

Inventor： Reinhold Bayerer

IPC: H01L23/12 ,  H01L23/52 ,  H01L25/16 ,  H01L39/02

CPC classification number: H01L23/3735 ,  C04B37/021 ,  C04B37/026 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/407 ,  H01L23/3731 ,  H01L23/3736 ,  H01L24/28 ,  H01L24/29 ,  H01L24/34 ,  H01L24/37 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/072 ,  H01L25/165 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48699 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/4061 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09554 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

Abstract translation: 公开了功率半导体模块。 一个实施例包括具有多个金属层和多个陶瓷层的多层基板，其中陶瓷层位于金属层之间。

公开(公告)号：US07433200B2

公开(公告)日：2008-10-07

申请号：US11797161

申请日：2007-05-01

Applicant: Jun Ishii ,  Yasunari Ooyabu

Inventor： Jun Ishii ,  Yasunari Ooyabu

IPC: H05K7/00

CPC classification number: H05K1/0259 ,  G11B5/484 ,  G11B5/486 ,  H05K1/056 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/09554

Abstract: A wired circuit board has a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer and including at least one pair of wires arranged in mutually spaced-apart and opposed relation having different potentials, a semiconductive layer formed on the insulating base layer to cover the conductive pattern and electrically connected to the metal supporting board on one side outside a region where the pair of wires are opposed, and an insulating cover layer formed on the semiconductive layer.

Abstract translation: 布线电路板具有金属支撑板，形成在金属支撑板上的绝缘基底层，形成在绝缘基底层上的导电图案，并且包括以相互间隔开和相对关系布置的具有不同电位的至少一对导线 形成在所述绝缘基底层上的半导体层，以覆盖所述导电图案并且在所述一对导线相对的区域的外侧的一侧电连接到所述金属支撑板，以及形成在所述半导体层上的绝缘覆盖层。

公开(公告)号：US20080099922A1

公开(公告)日：2008-05-01

申请号：US11554472

申请日：2006-10-30

Applicant: Noriaki Sakamoto

Inventor： Noriaki Sakamoto

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L21/00

CPC classification number: H01L23/49531 ,  H01L21/565 ,  H01L23/4334 ,  H01L23/49544 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/056 ,  H05K3/284 ,  H05K3/328 ,  H05K3/4084 ,  H05K3/44 ,  H05K2201/0382 ,  H05K2201/0385 ,  H05K2201/09554 ,  H05K2201/1034 ,  H05K2201/10924 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/20753 ,  H01L2924/2076 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A first insulating layer is formed on a front surface of a rectangular circuit board. Conductive patterns having a predetermined shape are formed on a front surface of the first insulating layer. A semiconductor element and a chip element are electrically connected to the conductive patterns by use of solder or conductive paste. The conductive patterns, the semiconductor element and the chip element which are formed on the front surface of the circuit board, are covered with a sealing resin. Pads on the circuit board and leads are connected to each other by use of thin metal wires.

Abstract translation: 第一绝缘层形成在矩形电路板的前表面上。 具有预定形状的导电图案形成在第一绝缘层的前表面上。 半导体元件和芯片元件通过使用焊料或导电膏电连接到导电图案。 形成在电路板的前表面上的导电图案，半导体元件和芯片元件被密封树脂​​覆盖。 电路板上的焊盘和引线通过使用细金属线相互连接。

公开(公告)号：US20080088975A1

公开(公告)日：2008-04-17

申请号：US11876320

申请日：2007-10-22

Applicant: Jeffry Bennin ,  Reid Danielson ,  Galen Houk

Inventor： Jeffry Bennin ,  Reid Danielson ,  Galen Houk

IPC: G11B15/64

CPC classification number: G11B5/4846 ,  G11B5/484 ,  G11B5/486 ,  H05K1/056 ,  H05K3/4046 ,  H05K3/44 ,  H05K2201/09554 ,  H05K2201/0969 ,  H05K2201/10234 ,  H05K2203/0195

Abstract: A method for forming an electrical interconnect to the spring metal layer in an integrated lead suspension or suspension component of the type having a multi-layer structure including a spring metal layer and a conductor layer separated by a dielectric insulator layer. The method includes forming an aperture through at least one of either the spring metal and conductor layers, and optionally through the dielectric layer, at an interconnect site. A first mass of malleable conductive metal is inserted into the aperture. The mass of metal is then coined to form a stud that engages at least the spring metal layer at the interconnect site.

Abstract translation: 一种用于在具有包括弹性金属层和由电介质绝缘体层隔开的导体层的多层结构的类型的集成铅悬浮或悬挂部件中形成与弹簧金属层的电互连的方法。 该方法包括在互连位置处通过弹簧金属和导体层中的至少一个，以及任选地通过介电层形成孔。 将第一质量的韧性导电金属插入孔中。 然后将金属质量打造成形成在互连位置处至少与弹簧金属层接合的螺柱。

公开(公告)号：US07353590B2

公开(公告)日：2008-04-08

申请号：US11224191

申请日：2005-09-12

Applicant: Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

Inventor： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC: H05K3/36

CPC classification number: H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Abstract translation: 提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路卡的方法。 光刻图形的金属填充通孔和电镀通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。 边框可以在卡的周围，包括从电介质层之一的边缘终止的金属层。 提供带有间隙孔的铜箔。 第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。 在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。 开发了通孔，在两个电介质层中对其进行图案化。 可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

公开(公告)号：US07342801B2

公开(公告)日：2008-03-11

申请号：US10835251

申请日：2004-04-29

Applicant: Gregory M. Jandzio ,  Anders P. Pedersen ,  Gary A. Rief ,  Walter M. Whybrew

Inventor： Gregory M. Jandzio ,  Anders P. Pedersen ,  Gary A. Rief ,  Walter M. Whybrew

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0243 ,  H01Q3/26 ,  H01Q21/0006 ,  H01Q21/0037 ,  H05K3/429 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/10553 ,  H05K2203/049 ,  Y10T29/49165

Abstract: A structural printed wiring board panel includes a multilayer printed wiring board having opposing, outer faces and interlayer interconnects that route RF, power and control signals. Connection areas are formed in or on at least on one face for connecting the interlayer interconnects and any electrical components. A metallic face sheet is secured onto at least one outer face, adding structural rigidity to the multilayer printed wiring board. A metallic face sheet can have apertures positioned to allow access to connection areas. RF components can be carried by a face sheet and operatively connected to connection areas. Antenna elements can be positioned on the same or an opposing face sheet and operatively connected to RF components to form a phased array printed wiring board (PWB) panel.

Abstract translation: 结构印刷线路板面板包括具有相对的外表面和层间互连的多层印刷线路板，其布置RF，功率和控制信号。 连接区域形成在至少一个面上或之上，用于连接层间互连和任何电气部件。 将金属面板固定在至少一个外表面上，为多层印刷线路板增加结构刚性。 金属面板可以具有定位成允许接近连接区域的孔。 RF部件可以由面板承载并且可操作地连接到连接区域。 天线元件可以定位在相同或相对的面板上并且可操作地连接到RF部件以形成相控阵列印刷线路板（PWB）面板。

公开(公告)号：US07342750B2

公开(公告)日：2008-03-11

申请号：US10870082

申请日：2004-06-16

Applicant: Chao-Hui Yang ,  Yen Fu ,  Li-Yan Zhu ,  Manny Hernandez ,  Ellis T. Cha ,  Yong Luo

Inventor： Chao-Hui Yang ,  Yen Fu ,  Li-Yan Zhu ,  Manny Hernandez ,  Ellis T. Cha ,  Yong Luo

IPC: G11B5/48

CPC classification number: G11B5/486 ,  G11B5/484 ,  H05K1/0228 ,  H05K1/056 ,  H05K3/4685 ,  H05K2201/09554 ,  H05K2201/0969 ,  H05K2201/097

Abstract: An externally wireless laminated suspension for a hard disk drive are disclosed. In one embodiment, the externally wireless laminated suspension has an insulating layer to electrically isolate a first and second electrical trace from a conductive support layer. The second electrical trace crosses over the first electrical trace. The first electrical trace may be made of a first part on one side of the second electrical trace and a second part on the opposite side of the electrical trace. A conductive island area may be patterned into the support layer. The conductive island area may electrically couple the first part of the first electrical trace to the second part. The number of crossover points that the first electrical trace has may equal the number of crossover points that the second electrical trace has.

Abstract translation: 公开了一种用于硬盘驱动器的外部无线层叠悬架。 在一个实施例中，外部无线层叠悬架具有绝缘层，以将第一和第二电迹线与导电支撑层电隔离。 第二电迹线穿过第一电迹线。 第一电迹线可以由第二电迹线的一侧上的第一部分和在电迹线的相对侧上的第二部分制成。 导电岛区域可以被图案化成支撑层。 导电岛区域可以将第一电迹线的第一部分电耦合到第二部分。 第一电迹线具有的交叉点的数量可以等于第二电迹线具有的交叉点的数量。

公开(公告)号：US20080052902A1

公开(公告)日：2008-03-06

申请号：US11976617

申请日：2007-10-25

Applicant: Keun-Ho Kim ,  Dek-Gin Yang ,  Jong-Guk Kim ,  Il-Kyoon Jeon ,  Eung-Suek Lee

Inventor： Keun-Ho Kim ,  Dek-Gin Yang ,  Jong-Guk Kim ,  Il-Kyoon Jeon ,  Eung-Suek Lee

IPC: H05K3/00

CPC classification number: H05K3/4641 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/056 ,  H05K3/4069 ,  H05K3/4608 ,  H05K3/4614 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit board and manufacturing method thereof. A printed circuit board has an insulation substrate, which includes an insulation layer, a circuit pattern formed on one side of the insulation layer, and an interlayer passage joined to the insulation layer and configured to electrically connect with the circuit pattern, and a heat-release layer, which is stacked on the other side of the insulation layer to be stacked on the insulation substrate, can provide a high heat-releasing effect and high bending strength, by means of inner layers or ground layers formed by the heat-release layers.

Abstract translation: 印刷电路板及其制造方法。 印刷电路板具有绝缘基板，该绝缘基板包括绝缘层，形成在绝缘层的一侧的电路图案，以及与该绝缘层接合并被构造为与电路图形电连接的层间通道， 层叠在绝缘层的另一方的层叠在绝缘基板上的剥离层能够通过由散热层形成的内层或接地层提供高散热效果和高弯曲强度 。

公开(公告)号：US20070295534A1

公开(公告)日：2007-12-27

申请号：US11812797

申请日：2007-06-21

Applicant: Jun Ishii ,  Yasunari Ooyabu ,  Visit Thaveeprungsriporn

Inventor： Jun Ishii ,  Yasunari Ooyabu ,  Visit Thaveeprungsriporn

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/0259 ,  G11B5/484 ,  G11B5/486 ,  H05K1/056 ,  H05K1/167 ,  H05K2201/09554 ,  Y10T428/1328 ,  Y10T428/1393 ,  Y10T428/256 ,  Y10T428/257

Abstract: A wired circuit board has a metal supporting board, an insulating layer formed on the metal supporting board, a conductive pattern formed on the insulating layer and having a pair of wires arranged in spaced-apart relation, and a semiconductive layer formed on the insulating layer and electrically connected to the metal supporting board and the conductive pattern. The conductive pattern has a first region in which a distance between the pair of wires is small and a second region in which the distance between the pair of wires is larger than that in the first region. The semiconductive layer is provided in the second region.

Abstract translation: 布线电路板具有金属支撑板，形成在金属支撑板上的绝缘层，形成在绝缘层上并具有间隔布置的一对电线的导电图案，以及形成在绝缘层上的半导体层 并且电连接到金属支撑板和导电图案。 导电图案具有第一区域，其中一对导线之间的距离小，并且一对导线之间的距离大于第一区域中的距离的第二区域。 半导体层设置在第二区域中。