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    Spin coat process for manufacturing a Z-directed component for a printed circuit board
    21.
    发明授权
    Spin coat process for manufacturing a Z-directed component for a printed circuit board 有权
    用于制造用于印刷电路板的Z指向部件的旋涂工艺

    公开(公告)号：US08658245B2

    公开(公告)日：2014-02-25

    申请号：US13222276

    申请日：2011-08-31

    Applicant: Paul Kevin Hall ,  Keith Bryan Hardin ,  Zachary Charles Nathan Kratzer ,  Qing Zhang

    Inventor： Paul Kevin Hall ,  Keith Bryan Hardin ,  Zachary Charles Nathan Kratzer ,  Qing Zhang

    IPC: B05D1/32 ,  B05D3/12

    CPC classification number: H05K1/184 ,  H01G2/06 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0248 ,  H05K1/0251 ,  H05K3/4046 ,  H05K2201/09645

    Abstract: A method for manufacturing a z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes depositing a liquid based material onto a top surface of a rotatable plate. The top surface of the rotatable plate has at least one cavity formed thereon that defines the shape of a layer of the z-directed component. The rotatable plate is spun to level a top surface of the liquid based material in the at least one cavity. The liquid based material is cured to form the layer of the z-directed component. A conductive material is applied to at least one surface of the formed layer. The z-directed component is formed including a stack of component layers that includes the formed layer.

    Abstract translation: 根据一个示例性实施例的用于制造用于插入到印刷电路板的安装孔中的z定向部件的方法包括将液体基材料沉积到可旋转板的顶表面上。 可旋转板的顶表面具有形成在其上的至少一个空腔，其限定z定向部件的层的形状。 旋转板旋转以在至少一个空腔中使基于液体的材料的顶表面平坦化。 固化液体基材料以形成z定向组分的层。 将导电材料施加到所形成的层的至少一个表面。 z引导分量被形成为包括一层包括所形成的层的组分层。

    CIRCUIT BOARD MULTI-FUNCTIONAL HOLE SYSTEM AND METHOD
    22.
    发明申请
    CIRCUIT BOARD MULTI-FUNCTIONAL HOLE SYSTEM AND METHOD 有权
    电路板多功能孔系统及方法

    公开(公告)号：US20140001150A1

    公开(公告)日：2014-01-02

    申请号：US13537361

    申请日：2012-06-29

    Applicant: Roy J. Lecesse

    Inventor： Roy J. Lecesse

    IPC: H05K3/00

    CPC classification number: H05K3/429 ,  C23C18/165 ,  C23C18/1653 ,  C23C18/38 ,  H05K3/42 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/09645 ,  H05K2203/0207 ,  H05K2203/1476

    Abstract: A method and system for constructing a printed circuit board with multifunctional holes. A first conductive material is deposited into a hole in a substrate to form a first plating on an inner surface of the hole. At least one outer portion of the hole is modified to have a larger diameter than the original hole and to remove the first conductive material from that outer portion. A seed material is deposited into the modified hole. An etchant is applied to the hole to non-mechanically remove the first conductive material from the unmodified portion of the hole. Another conductive material is deposited to into the modified hole that adheres to the seed material in the modified outer portion via to form a second plating at the outer portion.

    Abstract translation: 一种用于构造具有多功能孔的印刷电路板的方法和系统。 将第一导电材料沉积在基底中的孔中以在孔的内表面上形成第一电镀。 孔的至少一个外部部分被修改为具有比原始孔更大的直径并且从该外部部分移除第一导电材料。 种子材料沉积到修改的孔中。 将蚀刻剂施加到孔以从孔的未修改部分非机械地去除第一导电材料。 另一种导电材料被沉积到修饰的孔中，该修饰的孔粘附在改进的外部部分通孔中的种子材料上，以在外部部分形成第二电镀。

    Partitioned through-layer via and associated systems and methods
    23.
    发明授权
    Partitioned through-layer via and associated systems and methods 有权
    分层通过层和通过相关的系统和方法

    公开(公告)号：US08536046B2

    公开(公告)日：2013-09-17

    申请号：US13757295

    申请日：2013-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Teck Kheng Lee

    IPC: H01L21/44

    CPC classification number: H05K13/00 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09854 ,  H01L2924/00

    Abstract: Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.

    Abstract translation: 包括这种通孔和互连的分隔的过孔，互连和衬底在本文中公开。 在一个实施例中，衬底具有形成在非导电层的一部分中的非导电层和分隔通孔。 非导电层包括顶侧，底侧和在顶侧和底侧之间延伸的通孔，并且包括具有第一部分和第二部分的侧壁。 分隔通孔包括在侧壁的第一部分上的通孔内的第一金属互连和在侧壁的第二部分上的通孔内的第二金属互连，并与第一金属互连电隔离。 在另一个实施例中，第一金属互连通过通孔内的间隙与第二金属互连分开。

    PROCESS FOR PROVIDING ELECTRICAL CONNECTIONS WITH REDUCED VIA CAPACITANCE ON CIRCUIT BOARDS
    25.
    发明申请
    PROCESS FOR PROVIDING ELECTRICAL CONNECTIONS WITH REDUCED VIA CAPACITANCE ON CIRCUIT BOARDS 有权
    在电路板上通过电容降低提供电气连接的方法

    公开(公告)号：US20130111745A1

    公开(公告)日：2013-05-09

    申请号：US13289995

    申请日：2011-11-04

    Applicant: Eric R. Ao

    Inventor： Eric R. Ao

    IPC: H05K3/30

    CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K2201/09645 ,  Y10T29/49139 ,  Y10T29/49165

    Abstract: The present invention relates to circuit boards and, more specifically, a process for providing electrical connections with reduced via capacitance on circuit boards. In one embodiment, the present invention provides a method for providing an electrical connection between traces disposed on different layers of a circuit board, the method comprising forming in the circuit board a via hole that interconnects a first electrically conductive trace and a second electrically conductive trace. The via hole includes electrically conductive material thereon. The method further comprises removing a portion of the electrically conductive material from the via hole.

    Abstract translation: 本发明涉及电路板，更具体地说，涉及一种用于在电路板上提供减少的通孔电容的电连接的方法。 在一个实施例中，本发明提供了一种用于在布置在电路板的不同层上的迹线之间提供电连接的方法，所述方法包括在电路板中形成将第一导电迹线和第二导电迹线互连的通孔 。 通孔包括导电材料。 该方法还包括从通孔去除一部分导电材料。

    Partitioned through-layer via and associated systems and methods
    28.
    发明授权
    Partitioned through-layer via and associated systems and methods 有权
    分层通过层和通过相关的系统和方法

    公开(公告)号：US08367538B2

    公开(公告)日：2013-02-05

    申请号：US12898891

    申请日：2010-10-06

    Applicant: Teck Kheng Lee

    Inventor： Teck Kheng Lee

    IPC: H01L21/44

    CPC classification number: H05K13/00 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09854 ,  H01L2924/00

    Abstract: Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.

    Abstract translation: 包括这种通孔和互连的分隔的过孔，互连和衬底在本文中公开。 在一个实施例中，衬底具有形成在非导电层的一部分中的非导电层和分隔通孔。 非导电层包括在顶侧和底侧之间延伸的顶侧，底侧和通孔，并且包括具有第一部分和第二部分的侧壁。 分隔通孔包括在侧壁的第一部分上的通孔内的第一金属互连和在侧壁的第二部分上的通孔内的第二金属互连，并与第一金属互连电隔离。 在另一个实施例中，第一金属互连通过通孔内的间隙与第二金属互连分开。

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