公开(公告)号：US08304662B2

公开(公告)日：2012-11-06

申请号：US11806680

申请日：2007-06-01

Applicant: Akiyoshi Saitou ,  Takeshi Midorikawa ,  Toru Kuraishi ,  Chikayuki Kumagai ,  Masashi Fujimoto ,  Kenichiro Abe

Inventor： Akiyoshi Saitou ,  Takeshi Midorikawa ,  Toru Kuraishi ,  Chikayuki Kumagai ,  Masashi Fujimoto ,  Kenichiro Abe

IPC: H05K1/16

CPC classification number: H05K1/0224 ,  H01L2924/0002 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4661 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/0959 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0425 ,  H05K2203/063 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A buildup board includes a buildup layer having a multilayer structure and/or a core layer having a multilayer structure. The multilayer structure includes a signal wiring pattern, a pad connected to the signal wiring pattern, an insulating part arranged around the pad on the same layer as the pad, and a conductor arranged around the insulating part on the same layer as the pad. The multilayer structure has at least two different keepouts where the keepout is defined as a minimum interval between an outline of the pad and the conductor closest to the pad on the same layer.

Abstract translation: 堆积板包括具有多层结构的堆积层和/或具有多层结构的芯层。 多层结构包括信号布线图案，连接到信号布线图案的焊盘，与焊盘相同的层上布置在焊盘周围的绝缘部分，以及布置在与焊盘相同的层上的绝缘部分周围的导体。 所述多层结构具有至少两个不同的保持部，其中所述挡板被定义为所述焊盘的轮廓与最靠近所述焊盘在同一层上的导体之间的最小间隔。

公开(公告)号：US08294036B2

公开(公告)日：2012-10-23

申请号：US12410699

申请日：2009-03-25

Applicant: Shinichiro Kakei ,  Kenji Horino ,  Hitoshi Saita ,  Yasunobu Oikawa

Inventor： Shinichiro Kakei ,  Kenji Horino ,  Hitoshi Saita ,  Yasunobu Oikawa

IPC: H05K1/16 ,  H05K1/18

CPC classification number: H05K1/162 ,  H05K3/382 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2203/033

Abstract: In a dielectric element, the side faces are roughened so that the surface roughness Ra is 15 nm or greater. By this means, the area of contact between a glass epoxy resin substrate and insulating material is increased, adhesion with resin substrates is improved, and strength and reliability can be enhanced when buried between two resin substrates. In the dielectric element, the surface roughness Ra of side surfaces is 5000 nm or less, so that when burying the dielectric element between a glass epoxy resin substrate and insulating material, the occurrence of air bubbles between the surface of the dielectric element and the resin can be prevented.

Abstract translation: 在电介质元件中，侧面粗糙化，使得表面粗糙度Ra为15nm以上。 通过这种方式，玻璃环氧树脂基板和绝缘材料之间的接触面积增加，与树脂基板的粘合性提高，并且当埋在两个树脂基板之间时可以提高强度和可靠性。 在电介质元件中，侧面的表面粗糙度Ra为5000nm以下，因此当在玻璃环氧树脂基板和绝缘材料之间埋入电介质元件时，介电元件表面与树脂之间产生气泡 可以防止。

公开(公告)号：US08248816B2

公开(公告)日：2012-08-21

申请号：US11591021

申请日：2006-10-31

Applicant: Pat Fung

Inventor： Pat Fung

IPC: H05K1/14

CPC classification number: H05K1/116 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/182 ,  H05K3/429 ,  H05K2201/09718 ,  H05K2201/10189

Abstract: A method of creating a layout geometry for a multilayer printed circuit board is described. The method involves identifying a signal trace connected to a connector pin via. A antipad is selected for use in conjunction with the connector pin via, where the antipad is of a size selected to prevent interference with said signal trace.

Abstract translation: 描述了一种创建多层印刷电路板的布局几何形状的方法。 该方法包括识别连接到连接器引脚的信号迹线。 选择一个止动件用于与连接器针脚连接使用，其中止动件的尺寸被选择以防止与所述信号迹线的干扰。

公开(公告)号：US08226438B2

公开(公告)日：2012-07-24

申请号：US12789621

申请日：2010-05-28

Applicant: Thomas S. Cohen ,  Marc B. Cartier, Jr. ,  Mark W. Gailus

Inventor： Thomas S. Cohen ,  Marc B. Cartier, Jr. ,  Mark W. Gailus

IPC: H01R13/648

CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

Abstract translation: 中平面具有连接第一差分连接器的接触端的第一侧和与第二差分连接器的接触端连接的第一侧相对的第二侧。 中平面包括从第一侧延伸到第二侧的多个通孔，其中通孔在第一侧上提供第一信号发射，而第二信号在第二侧上发射。 第一信号发射被设置成多行，每行具有沿着第一线的第一信号发射，并且第一信号沿着基本上平行于第一线的第二线发射。 第二信号发射被提供在多列中，每列具有沿着第三线的第二信号发射，而第二信号沿着基本上平行于第三线的第四线发射。

公开(公告)号：US08153907B2

公开(公告)日：2012-04-10

申请号：US12010437

申请日：2008-01-24

Applicant: Dae-Hyun Park ,  Han Kim ,  Mi-Ja Han ,  Ja-Bu Koo

Inventor： Dae-Hyun Park ,  Han Kim ,  Mi-Ja Han ,  Ja-Bu Koo

IPC: H05K1/11

CPC classification number: H05K1/0236 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09781 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T428/12465

Abstract: An electromagnetic bandgap structure and a printed circuit board that solve a mixed signal problem are disclosed. In accordance with embodiments of the present invention, the electromagnetic bandgap structure includes a first metal layer; a first dielectric layer, stacked in the first metal layer; a second metal layer, stacked in the first dielectric layer, and having a holed formed at a position of the second dielectric layer; a second dielectric layer, stacked in the second metal layer; a metal plate, stacked in the second dielectric layer; a first via, penetrating the hole formed in the second metal layer and connecting the first metal layer and the metal plate; a third dielectric layer, stacked in the metal plate and the second dielectric layer; a third metal layer, stacked in the third dielectric layer; and a second via, connecting the second metal layer to the third metal layer.

Abstract translation: 公开了一种解决混合信号问题的电磁带隙结构和印刷电路板。 根据本发明的实施例，电磁带隙结构包括第一金属层; 第一介电层，堆叠在第一金属层中; 第二金属层，堆叠在第一介电层中，并且具有形成在第二介电层的位置的孔; 第二介电层，堆叠在第二金属层中; 金属板，堆叠在第二介电层中; 穿过形成在第二金属层中的孔并连接第一金属层和金属板的第一通孔; 第三电介质层，堆叠在所述金属板和所述第二介电层中; 第三金属层，堆叠在第三介电层中; 以及将第二金属层连接到第三金属层的第二通孔。

公开(公告)号：US08130507B2

公开(公告)日：2012-03-06

申请号：US12409143

申请日：2009-03-23

Applicant: Makoto Origuchi ,  Tsuneaki Takashima

Inventor： Makoto Origuchi ,  Tsuneaki Takashima

IPC: H05K7/00

CPC classification number: H05K1/185 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A component built-in wiring board is provided. The component built-in wiring board 10 includes a core substrate 11, a first component 61, a first built-up layer 31 and a capacitor 101. The core substrate 11 has a housing hole 90 and the first component 61 is housed in the housing hole 90. A component mounting region 20 capable of mounting a second component 21 is provided in a surface 39 of the first built-up layer 31. The capacitor 101 has electrode layers 102 and 103 and a dielectric layer 104. The capacitor 101 is embedded in the first built-up layer 31 such that a first front surface 105 and a second front surface 106 in the electrode layer 102 and a first front surface 107 and a second front surface 108 in the electrode layer 103 are disposed in parallel with the surface 39 of the first built-up layer 31.

Abstract translation: 提供组件内置接线板。 部件内置布线板10包括芯基板11，第一部件61，第一累积层31和电容器101.芯基板11具有容纳孔90，第一部件61容纳在壳体 在第一累积层31的表面39中设置能够安装第二部件21的部件安装区域20.电容器101具有电极层102和103以及电介质层104.电容器101被嵌入 在第一堆叠层31中使得电极层102中的第一前表面105和第二前表面106以及电极层103中的第一前表面107和第二前表面108平行于该表面 39是第一组合层31。

公开(公告)号：US20120017437A1

公开(公告)日：2012-01-26

申请号：US13252256

申请日：2011-10-04

Applicant: Rabindra N. Das ,  Kostas I. Papathomas ,  Voya R. Markovich

Inventor： Rabindra N. Das ,  Kostas I. Papathomas ,  Voya R. Markovich

IPC: H05K3/40

CPC classification number: H05K1/0313 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/16 ,  B23K2103/172 ,  B23K2103/52 ,  H01B1/22 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/097 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0257 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0425 ,  H05K2203/1152 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.

Abstract translation: 一种电路化基板，包括用于提供电连接的导电浆料。 在一个实施方案中，糊状物包括包含纳米颗粒的金属组分，并且可以包括附加元素，例如焊料或其它金属微粒，以及导电聚合物和有机物。 糊料组合物的颗粒烧结并且根据添加的另外的元素而熔化，因为层压，从而形成通过糊料的有效连续的电路。 还提供了制造这种基板的方法，以及利用该基板并且包括诸如与其耦合的半导体芯片的电子部件的电组件。

公开(公告)号：US08094429B2

公开(公告)日：2012-01-10

申请号：US12488780

申请日：2009-06-22

Applicant: Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai

Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC: H01G4/228

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/232 ,  H01G4/30 ,  H01G4/35 ,  H01L28/86 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09718 ,  Y10T29/43

Abstract: A capacitor device may include a first electrode, a second electrode, a third electrode, a first dielectric layer, and a second dielectric layer. The first electrode may be coupled with a first terminal of the capacitor device. The second electrode is under the first electrode and may be coupled with a second terminal of the capacitor device. The second electrode may be electrically isolated from the first electrode. The third electrode is under the first electrode and the second electrode and may be electrically isolated from the second electrode and electrically coupled with the first electrode. The first dielectric layer has a first dielectric constant and may be sandwiched between the first electrode and the second electrode. The second dielectric layer may have a second dielectric constant and may be sandwiched between the second electrode and the third electrode. In one embodiment, the second dielectric constant is at least five times larger than the first dielectric constant.

Abstract translation: 电容器装置可以包括第一电极，第二电极，第三电极，第一电介质层和第二电介质层。 第一电极可以与电容器装置的第一端子耦合。 第二电极位于第一电极下方并且可以与电容器装置的第二端子耦合。 第二电极可以与第一电极电隔离。 第三电极在第一电极和第二电极之下，并且可以与第二电极电隔离并与第一电极电耦合。 第一电介质层具有第一介电常数并且可夹在第一电极和第二电极之间。 第二电介质层可以具有第二介电常数并且可以夹在第二电极和第三电极之间。 在一个实施例中，第二介电常数比第一介电常数大至少五倍。

公开(公告)号：US08085545B2

公开(公告)日：2011-12-27

申请号：US12453720

申请日：2009-05-20

Applicant: Eun-Seok Song

Inventor： Eun-Seok Song

IPC: H05K7/00

CPC classification number: H05K1/0233 ,  H01L23/552 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K2201/086 ,  H05K2201/09718 ,  H05K2201/09781 ,  H01L2924/00

Abstract: A structure for blocking electromagnetic interference (EMI) may include at least one electromagnetic wave inducing member and an electromagnetic wave filtering member. The at least one electromagnetic wave inducing member may be provided to an electronic device to induce an electromagnetic wave applied to the electronic device. The electromagnetic wave filtering member may be provided to the electronic device to filter the electromagnetic wave induced by the at least one electromagnetic wave inducing member. Thus, the electromagnetic wave filtering member may remove the electromagnetic wave concentrated on the at least one electromagnetic wave inducing member, so that the electromagnetic wave applied to the electronic device may be effectively removed. As a result, circuits in the electronic device may be protected from the EMI.

Abstract translation: 用于阻挡电磁干扰（EMI）的结构可以包括至少一个电磁波感应构件和电磁波滤波构件。 可以将至少一个电磁波感应构件提供给电子设备以引起施加到电子设备的电磁波。 电磁波滤波构件可以设置在电子设备中，以对由至少一个电磁波诱导构件所引起的电磁波进行滤波。 因此，电磁波滤波构件可以去除集中在至少一个电磁波感应构件上的电磁波，从而可以有效地去除施加到电子装置的电磁波。 因此，可以保护电子设备中的电路不受EMI影响。

公开(公告)号：US08085112B2

公开(公告)日：2011-12-27

申请号：US13187910

申请日：2011-07-21

Applicant: Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

Inventor： Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

IPC: H03H7/38

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; the length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

Abstract translation: 根据一个实施例，形成在多层基板中连接通孔结构和平面传输线的宽带转变，作为信号通孔焊盘和布置在相同导体层处的平面传输线之间的中间连接。 过渡的横向尺寸等于一端的通孔焊盘直径和另一端的带宽度; 转换的长度可以等于平面传输线方向上的间隙孔的特征尺寸，或者根据通过三维全波模拟获得的数字图，定义为在时域中提供极小的超额感抗 。