公开(公告)号：US20030033108A1

公开(公告)日：2003-02-13

申请号：US10029571

申请日：2001-12-20

Inventor： Eiji Takahashi ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Osamu Shibata ,  Shinichi Tanimoto ,  Takeshi Nakayama

IPC: G06F019/00

CPC classification number: G06F17/5068 ,  H05K1/0275 ,  H05K1/0298 ,  H05K1/114 ,  H05K2201/09627 ,  H05K2201/09772 ,  H05K2201/10151

Abstract: A signal line, being in a six-layer board and connecting terminal 102 of component 101 with terminal 115 of component 114, requires tamper-resistance. The signal line is composed of foil 103 on an outside layer, a via 104, foil 111 on the third layer, via 105, foil 112 on the fourth layer, via 106, and foil 113 on the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foil 103 and an end of via 104 are placed under component 101 on first layer 116, an end of via 105 is placed under component 107 on layer 116, an end of via 106 is placed under component 108 on layer 116, the other end of via 104 is placed under component 109 on sixth layer 121, the other end of via 105 is placed under component 110 on layer 121, and foil 113 and the other end of via 106 are placed under component 114 on layer 121.

Abstract translation: 在组件101的六层板和连接端子102与元件114的端子115之间的信号线需要防篡改。 信号线由外层的箔103，通孔104，第三层上的箔111，通孔105，第四层上的箔112，第106层和第六层上的箔113组成。 存在于外层的信号线部分都隐藏在电路元件下面。 箔103和通孔104的末端放置在第一层116上的部件101下方，通孔105的端部放置在层116上的部件107的下方，通孔106的端部放置在层116上的部件108的下方，另一端 通孔104被放置在第六层121上的部件109的下方，通孔105的另一端被放置在层121上的部件110下方，并且箔113和通孔106的另一端放置在层121上的部件114下方。

公开(公告)号：US20010024360A1

公开(公告)日：2001-09-27

申请号：US09800582

申请日：2001-03-08

Applicant: FUJI XEROX CO., LTD.

Inventor： Masayuki Hirata ,  Osamu Ueno

IPC: H05K007/02

CPC classification number: H05K9/0039 ,  H05K1/0225 ,  H05K1/0233 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/1006 ,  H05K2201/10689

Abstract: A printed wiring board in which noise components at a high frequency side of a power supply voltage can be eliminated, and undesired radiation noisewhich is newly generated can be suppressed, such that noise can be greatly reduced overall. The printed wiring board includes a first signal layer, a GND layer, a power source layer and a second signal layer. A sub-power source layer is provided on a same layer as a main power source layer. The sub-power source layer is formed in a substantially oval shape at a predetermined position in a substantially oval opening in the main power source layer, such that it is not in direct contact with the main power source layer. Power supply voltage is supplied from the main power source layer through an L-type filter.

Abstract translation: 可以抑制能够消除电源电压的高频侧的噪声成分的新印刷布线板，并且可以抑制新生成的不期望的放射线，使得整体上可以大大降低噪声。 印刷电路板包括第一信号层，GND层，电源层和第二信号层。 子电源层设置在与主电源层相同的层上。 子电源层在主电源层中的大致椭圆形的开口中的预定位置处形成为大致椭圆形状，使得它不与主电源层直接接触。 电源电压由主电源层通过L型滤波器供电。

公开(公告)号：US5892274A

公开(公告)日：1999-04-06

申请号：US900243

申请日：1997-07-24

Applicant: Milton L. Buschbom

Inventor： Milton L. Buschbom

IPC: H01L23/16 ,  H01L23/433 ,  H05K1/02 ,  H01L23/48 ,  H01L29/40 ,  H01L39/00

CPC classification number: H05K1/0243 ,  H01L23/16 ,  H01L23/4334 ,  H05K1/0218 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10477 ,  H05K2201/10689

Abstract: The invention is to a combination of a semiconductor device and a ground plane on a printed wiring board to provide a controlled impedance signal lead. A printed wiring board has a ground plane layer, and a semiconductor device having a down-set, or deep down-set, lead frame die mounting pad is mounted on the printed wiring board above the ground plane layer. The leads of the semiconductor device form a transmission line in combination with the ground plane, when the leads are placed a controlled distance above the ground plane.

Abstract translation: 本发明是在印刷电路板上的半导体器件和接地平面的组合，以提供受控的阻抗信号引线。 印刷电路板具有接地层，并且在接地层上方的印刷电路板上安装有具有下降或下降的引线框模具安装焊盘的半导体器件。 当引线被放置在接地平面上方受控的距离时，半导体器件的引线与接地平面组合形成传输线。

公开(公告)号：US5509599A

公开(公告)日：1996-04-23

申请号：US194018

申请日：1994-02-09

Applicant: Hans-Bodo Laue

Inventor： Hans-Bodo Laue

IPC: H05K1/14 ,  H05K1/16 ,  H05K3/34 ,  H05K3/36 ,  B23K31/02

CPC classification number: H05K3/363 ,  H05K1/141 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/09772 ,  H05K2201/10666 ,  H05K2201/10689 ,  H05K2203/0455 ,  H05K3/3436 ,  H05K3/368

Abstract: Hybrid circuits are usually secured with contact pins (combs) on printed circuit boards by undergoing a flow solder bath. Further, surface-mountable components are soldered on the printed circuit board in a furnace. Two soldering processes are necessary for this purpose. The method of the invention avoids one of the soldering processes by applying through-contacted bores on the carrier substrate of the hybrid circuit. These through-contacted bores are put in place onto solder surfaces of the printed circuit board having a paste solder and the overall arrangement is soldered in a furnace.

Abstract translation: 混合电路通常通过经受流动焊锡浴的方式用印刷电路板上的接触针（梳子）固定。 此外，可表面安装的部件在炉中焊接在印刷电路板上。 为此，需要两个焊接工艺。 本发明的方法通过在混合电路的载体衬底上施加通孔来避免焊接过程之一。 将这些通孔连接到具有糊状焊料的印刷电路板的焊接表面上，并且整体布置被焊接在炉中。

公开(公告)号：US4945451A

公开(公告)日：1990-07-31

申请号：US254260

申请日：1988-09-16

Applicant: Pierre Gohl ,  Raymond Llabres ,  Pascal Malgouires

Inventor： Pierre Gohl ,  Raymond Llabres ,  Pascal Malgouires

IPC: H05K1/02 ,  H05K3/34 ,  H05K7/20

CPC classification number: H05K7/205 ,  H05K1/0209 ,  H05K2201/066 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K3/3447

Abstract: The invention discloses a printed circuit card on which is welded at least an electronic component box as well as a thermal dissipator for dissipating the heat emitted by the component box. The component box and the thermal dissipator are respectively provided with clips and lugs which are engaged and welded in respective holes drilled in the card. A thermal drainage metallic area provided on a zone of the card located under the box forms a thermal adduction path between the box and the lugs of the thermal dissipator. This thermal drainage metallic area is further connected to a clip ensuring a privileged thermal drainage of the electronic component box.

Abstract translation: 本发明公开了一种印刷电路卡，其上焊接有至少一个电子元件盒以及散热器，用于散发由元件盒发出的热量。 组件箱和散热器分别设置有夹子和凸耳，它们被接合并焊接在卡中钻出的各个孔中。 位于盒下方的卡的区域上提供的散热金属区域在箱体和散热器的凸耳之间形成热介导路径。 该散热金属区域进一步连接到夹子上，确保电子元件箱的特殊排热。

公开(公告)号：US4047132A

公开(公告)日：1977-09-06

申请号：US698021

申请日：1976-06-21

Applicant: Ignacy Krajewski

Inventor： Ignacy Krajewski

IPC: H01P3/08 ,  H01P5/02 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01P3/088 ,  H01P5/02 ,  H05K1/0218 ,  H05K1/0253 ,  H05K1/029 ,  H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0298 ,  H05K2201/09381 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2203/175

Abstract: The present invention is concerned with multilayer printed circuit boards which have more than a single plane of interconnection conductors spaced away from a common plane, such as an earth or power plane. In such a case the conductors of the interconnection layers form transmission lines having respectively different impedances, depending on their distances from the common plane. The invention contemplates a pattern of conductive areas distributed over one of the surfaces of the multilayer board, the surface chosen lying on the opposite side of the planes of conductors from the common plane, the pattern configuration being chosen more nearly to equalize the impedances of the conductors. The areas of the pattern are preferably connected to the common plane.

Abstract translation: 本发明涉及多层印刷电路板，该多层印刷电路板具有多于一个平面的互连导体，与公共平面（例如地球或电源平面）间隔开。 在这种情况下，互连层的导体根据它们与公共平面的距离而形成具有各自不同阻抗的传输线。 本发明考虑了分布在多层板的一个表面上的导电区域的图案，该表面被选择在与公共平面的导体平面相对的一侧上，该图形配置被选择得更接近于均衡该多层板的阻抗 导体 图案的区域优选地连接到公共平面。

公开(公告)号：US3621112A

公开(公告)日：1971-11-16

申请号：US3621112D

申请日：1970-10-28

Applicant: GEN ELECTRIC

Inventor： STICKLEY BERYL C ,  TUTLE EDWARD G

IPC: H05K3/30 ,  H05K5/00 ,  H05K5/06

CPC classification number: H05K5/0095 ,  H05K3/306 ,  H05K2201/09772 ,  H05K2201/10568 ,  H05K2201/10969 ,  H05K2201/2036 ,  H05K2203/168

Abstract: A housing for electrical components that is suitable for mounting on printed circuit boards or other supporting members to be used in electrical-electronic equipment. The housing has a generally regular configuration (preferably rectangular), is enclosed on all sides, and preferably is fabricated from electrically conductive and ferromagnetic material. At least one surface of the housing (generally the bottom) has a plurality of housing supporting projections, preferably in the form of integral embossments, extending a predetermined distance for raising the housing above the surface of the printed circuit board or other supporting member a sufficient amount to provide for further processing or use such as to accommodate a cleaning or cooling flow of fluid. The projections are irregularly arrayed with respect to the sides of the housing and provide both tactile and visual indicators for facilitating proper alignment of the housing during placement on a printed circuit board or other supporting member. A plurality of electrically conductive leads extend through insulated openings in the bottom of the housing and are located at the intersections of an equally spaced grid system. The projections extending from the bottom of the housing are positioned so as to be located at selected spots corresponding to the intersections of the same equally spaced grid system that locates the electrically conductive leads. A greater number of the projections are formed on one side of the housing than are formed on the other in order to provide the irregularity in the array of projections required to facilitate alignment of the component during placement on a printed circuit board or other supporting member. Grounding strips of conductive material may be attached to the sides of the housing and where so attached, are so positioned relative to the intersections of the same equally spaced grid system locating the electrically conductive leads and projections as to fit into a logical extension of the equally spaced grid system. The sides of the housing may be hermetically sealed closed to provide a protective environment for the electrical components contained therein.

公开(公告)号：US10008757B2

公开(公告)日：2018-06-26

申请号：US15394868

申请日：2016-12-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kunitoshi Hanaoka

IPC: H01P1/00 ,  H01P5/18 ,  H03H7/38 ,  H04B1/04 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H02M1/00

CPC classification number: H01P5/18 ,  H01P5/184 ,  H01P5/187 ,  H02M1/00 ,  H03H7/38 ,  H04B1/04 ,  H05K1/0243 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/09772 ,  H05K2201/1003

Abstract: An inductor component is disposed outside a multilayer substrate, and thus a directional coupler defined by an internal wiring electrode and a coil electrode within the inductor component that is mounted on a pair of land electrodes, the multilayer substrate significantly reduces or prevents interference with other high-frequency circuit elements disposed in or on the multilayer substrate. Additionally, if a plurality of inductor components having different inductor characteristics are prepared, a high-frequency module including the multilayer substrate capable of defining the directional coupler whose characteristics are able to adjusted with ease is able to be provided simply by selecting the desired inductor component from the inductor components and replacing that inductor component.

公开(公告)号：US08101870B2

公开(公告)日：2012-01-24

申请号：US12393642

申请日：2009-02-26

Applicant: Norihiro Ishii

Inventor： Norihiro Ishii

IPC: H05K1/16

CPC classification number: H05K3/305 ,  H01L2224/32225 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/09572 ,  H05K2201/09772 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/043 ,  Y02P70/613 ,  Y10T29/4913

Abstract: A method for manufacturing a printed circuit board. The method includes: preparing a printed wiring board, the printed wiring board comprising through holes and a plurality of electrode pads; coating surfaces of the plurality of electrode pads and surfaces of the through holes on an one side of the printed wiring board with a bonding material; mounting a semiconductor package on the printed wiring board such that a plurality of bumps on a surface of the semiconductor package corresponds to the plurality of electrode pads; bonding the bumps to the electrode pads by heating the printed wiring board on which the semiconductor package is mounted; and filling a space between the semiconductor package and the printed wiring board with a filler material.

Abstract translation: 一种印刷电路板的制造方法。 该方法包括：制备印刷线路板，印刷线路板包括通孔和多个电极焊盘; 在印刷电路板的一侧用接合材料涂覆多个电极焊盘的表面和通孔的表面; 将半导体封装安装在所述印刷电路板上，使得所述半导体封装的表面上的多个凸块对应于所述多个电极焊盘; 通过加热其上安装有半导体封装的印刷线路板将凸块接合到电极焊盘; 以及用填充材料填充半导体封装和印刷线路板之间的空间。

公开(公告)号：US07838998B2

公开(公告)日：2010-11-23

申请号：US11560076

申请日：2006-11-15

Applicant: Takashi Ozawa ,  Yasushi Araki ,  Masatoshi Nakamura ,  Seiji Sato

Inventor： Takashi Ozawa ,  Yasushi Araki ,  Masatoshi Nakamura ,  Seiji Sato

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/73203 ,  H05K3/305 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613

Abstract: A mounting substrate for mounting a semiconductor chip in a flip chip manner, having a plurality of connection pads to which the semiconductor chip is connected, an insulating pattern formed so as to cover a part of the connection pads, and a plurality of dummy patterns for controlling a flow of an underfill infiltrated below the semiconductor chip, characterized in that the plurality of dummy patterns are arranged in staggered lattice shape.

Abstract translation: 一种用于以倒装芯片方式安装半导体芯片的安装基板，具有连接半导体芯片的多个连接焊盘，形成为覆盖连接焊盘的一部分的绝缘图案，以及多个用于 控制渗透在半导体芯片下方的底部填充物的流动，其特征在于，所述多个虚拟图案以交错的格子形状布置。