公开(公告)号：US20170133307A1

公开(公告)日：2017-05-11

申请号：US15159212

申请日：2016-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni Ziglioli

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0538 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15747 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0295 ,  H05K1/112 ,  H05K3/107 ,  H05K3/205 ,  H05K3/4015 ,  H05K3/4046 ,  H05K2201/09409 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/1189 ,  H05K2203/143 ,  H05K2203/1461 ,  H05K2203/1476 ,  H05K2203/308 ,  H01L2224/45099

Abstract: A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.

公开(公告)号：US09521748B1

公开(公告)日：2016-12-13

申请号：US14565267

申请日：2014-12-09

Applicant: Multek Technologies Ltd.

Inventor： Mark Bergman ,  Joan K. Vrtis

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H05K3/22

CPC classification number: H05K1/0271 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/0386 ,  H05K1/0393 ,  H05K1/144 ,  H05K1/148 ,  H05K3/22 ,  H05K3/4691 ,  H05K2201/0137 ,  H05K2201/05 ,  H05K2201/058 ,  H05K2201/09945 ,  H05K2201/0999 ,  H05K2201/2009

Abstract: Mechanical measures strengthen a flexible circuit board or deformable electronic by manipulating the location and/or intensity of the stress concentration or to limit bending, torsion, and stretching. A material layer is patterned onto the flexible circuit board with a specific pattern and place of deposition in order to modify the stress concentration and profile of the circuit board and increase its overall strength. The material layer may be configured to modify the stress concentrations during bending away from the weak points in the assembly or to spread the stress during bending by increasing the radius of the bend curvature and therefore decreasing the chance of mechanical failure.

Abstract translation: 机械措施通过操纵应力集中的位置和/或强度或限制弯曲，扭转和拉伸来加强柔性电路板或可变形电子。 将材料层图案化到具有特定图案和沉积位置的柔性电路板上，以便改变电路板的应力集中和轮廓并增加其整体强度。 材料层可以被配置为在远离组件中的弱点的过程中修改弯曲期间的应力集中，或者通过增加弯曲曲率半径来扩展弯曲过程中的应力，从而降低机械故障的机会。

公开(公告)号：US20070212521A1

公开(公告)日：2007-09-13

申请号：US10593622

申请日：2005-03-29

Applicant: Hisami Bessho ,  Hideyuki Sato ,  Akio Sato ,  Masatsugu Shimomura ,  Masaru Tanaka ,  Hiroshi Yabu

Inventor： Hisami Bessho ,  Hideyuki Sato ,  Akio Sato ,  Masatsugu Shimomura ,  Masaru Tanaka ,  Hiroshi Yabu

IPC: B32B3/10

CPC classification number: H01R12/7076 ,  C09J7/22 ,  C09J7/26 ,  C09J2201/128 ,  C09J2201/602 ,  H01R13/2414 ,  H05K3/323 ,  H05K2201/0116 ,  H05K2201/09945 ,  H05K2201/10378 ,  Y10T428/24322

Abstract: To provide an anisotropic conductive film which can respond to increasing pitch reduction of connection targets while maintaining connection reliability, and can be manufactured at a lower cost than conventional, and to provide a method of manufacturing the same. The anisotropic conductive film is provided with a porous film consisting of polymer, having numerous holes penetrating in a film thickness direction, the holes being in a honeycomb arrangement and having inner wall surfaces which curve outwards, a conductive material that fills the holes in the porous film, and an adhesive layer coated on both surfaces of the porous film. The porous film is formed by leaving a supporting substrate on which cast is a polymer solution where a polymer is dissolved in a hydrophobic, volatile organic solvent, under high humidity conditions.

Abstract translation: 为了提供能够对维持连接可靠性的连接目标的减小的增加作出响应的各向异性导电膜，并且可以以比传统的更低的成本制造并提供其制造方法。 各向异性导电膜设置有由聚合物组成的多孔膜，其具有沿膜厚度方向穿透的多个孔，该孔为蜂窝结构，并且具有向外弯曲的内壁表面，填充多孔的孔的导电材料 膜和涂覆在多孔膜的两个表面上的粘合剂层。 多孔膜通过在高湿度条件下留下支撑基底而形成，其上浇注聚合物溶液，其中聚合物溶解在疏水性挥发性有机溶剂中。

公开(公告)号：US06977025B2

公开(公告)日：2005-12-20

申请号：US10388441

申请日：2003-03-17

Applicant: Ciaran Bernard McArdle ,  Rory Brian Barnes

Inventor： Ciaran Bernard McArdle ,  Rory Brian Barnes

IPC: G03F7/34 ,  H01R4/04 ,  H05K3/32 ,  B32B31/00

CPC classification number: H01R4/04 ,  G03F7/34 ,  H01L2224/293 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K3/323 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2203/0769 ,  H05K2203/104 ,  Y10T428/24802 ,  H01L2924/00

Abstract: The invention provides a method of forming a monolayer of substantive particles including the steps of applying to a substrate a curable composition having substantive particles contained therein, the substantive particles having a particle size on at least one dimension thereof of at least 1 micrometer and being in two or more groups of different sizes; exposing the substantive particle-containing curable composition to a source of energy suitable for effecting polymerization of the curable composition for a sufficient time to effect polymerization of a layer of the curable composition having a thickness of no more than 50% of the height of the largest substantive particles; and optionally, removing uncured curable composition. The invention also provides a method of forming a monolayer of substantive particles in a non-random array where the curable composition comprises a ferrofluid composition. The latter method further comprises the step of subjecting the particle-containing curable ferrofluid composition to a magnetic field for a sufficient time to array the particles in a non-random manner in the composition prior to the exposure.

Abstract translation: 本发明提供了一种形成单层实质性颗粒的方法，包括以下步骤：将具有其中所含的实质性颗粒的可固化组合物施用于基材，所述实体颗粒的至少一个尺寸的颗粒尺寸至少为1微米， 两组或两组以上不同大小; 将含有实质的含颗粒的可固化组合物暴露于适于实现可固化组合物聚合足够时间的能量源，以实现可固化组合物层的厚度不超过最大厚度的50％ 实质粒子 并且任选地，除去未固化的可固化组合物。 本发明还提供了以非随机阵列形成单层实质性颗粒的方法，其中可固化组合物包含铁磁流体组合物。 后一种方法还包括以下步骤：使含有颗粒的可固化铁磁体组合物经历足够的时间以在曝光之前以非随机方式将组合物排列在组合物中。

公开(公告)号：US06797616B2

公开(公告)日：2004-09-28

申请号：US10225907

申请日：2002-08-21

Applicant: Larry D. Kinsman

Inventor： Larry D. Kinsman

IPC: H01L2144

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09945 ,  H01L2924/00

Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.

公开(公告)号：US20030067074A1

公开(公告)日：2003-04-10

申请号：US09974947

申请日：2001-10-10

Inventor： Larry D. Kinsman

IPC: H01L023/52

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09945 ,  H01L2924/00

Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.

Abstract translation: 本发明涉及一种用于连接放置在电路板的相对侧上的集成电路的装置和方法，该集成电路通过利用嵌入电路板中的导电元件并从板的一个表面延伸到另一个表面。 导电迹线沿着电路板的表面从导电元件延伸到集成电路。 导电迹线可以由多个导电层形成。

公开(公告)号：US5879530A

公开(公告)日：1999-03-09

申请号：US865129

申请日：1997-05-29

Applicant: Patrice Caillat

Inventor： Patrice Caillat

IPC: H01L21/68 ,  H01L23/492 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H05K3/40 ,  H05K3/42 ,  C25D5/02 ,  B05D1/32 ,  B05D1/36 ,  C25D5/50

CPC classification number: H01L21/6835 ,  H01L23/4922 ,  H01L23/49827 ,  H05K3/3436 ,  H01L2221/68345 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K2201/09563 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/0733 ,  H05K3/303 ,  H05K3/3463 ,  H05K3/4038 ,  H05K3/423 ,  Y02P70/613 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/2804 ,  Y10T428/2848

Abstract: This self-supported, anisotropic conductive film has a partly annealed polymer layer (46) containing through holes, nail-shaped conductive elements (51) filling the through holes, having a central portion and ends, and the central portion of the nails is made from a hard material (52) and each end respectively of a first and a second meltable materials (44, 54).

Abstract translation: 这种自支撑的各向异性导电膜具有包含通孔的部分退火的聚合物层（46），填充通孔的钉状导电元件（51），具有中心部分和端部，并且使指甲的中心部分 从第一和第二可熔融材料（44,54）的硬质材料（52）和各个端部分别接合。

公开(公告)号：US5681647A

公开(公告)日：1997-10-28

申请号：US538343

申请日：1995-10-03

Applicant: Patrice Caillat

Inventor： Patrice Caillat

IPC: H01L21/68 ,  H01L23/492 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H05K3/40 ,  H05K3/42 ,  B32B9/00

CPC classification number: H01L21/6835 ,  H01L23/4922 ,  H01L23/49827 ,  H05K3/3436 ,  H01L2221/68345 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K2201/09563 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/0733 ,  H05K3/303 ,  H05K3/3463 ,  H05K3/4038 ,  H05K3/423 ,  Y02P70/613 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/2804 ,  Y10T428/2848

Abstract: This self-supported, anisotropic conductive film has a partly annealed polymer layer (46) containing through holes, nail-shaped conductive elements (51) filling said through holes, having a central portion and ends, and the central portion of the nails is made from a hard material (52) and each end respectively of a first and a second meltable materials (44, 54).

Abstract translation: 这种自支撑的各向异性导电膜具有包含通孔的部分退火的聚合物层（46），填充具有中心部分和末端的所述通孔的钉状导电元件（51），并且使钉子的中心部分 从第一和第二可熔融材料（44,54）的硬质材料（52）和各个端部分别接合。

公开(公告)号：US5544018A

公开(公告)日：1996-08-06

申请号：US227315

申请日：1994-04-13

Applicant: Scott C. Sommerfeldt ,  Thomas W. Rudwick, III ,  Robert F. Miracky

Inventor： Scott C. Sommerfeldt ,  Thomas W. Rudwick, III ,  Robert F. Miracky

IPC: H01L23/538 ,  H05K1/00 ,  H05K3/46 ,  H05K1/11

CPC classification number: H01L23/5382 ,  H05K1/0287 ,  H05K1/029 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K1/0298 ,  H05K2201/09345 ,  H05K2201/09945 ,  H05K2203/175 ,  H05K3/467

Abstract: Provided is an electrical interconnect cell intermittently spaced across a substrate to form an interconnect device or structure. The interconnect device is fully customizable or programmable upon the upper surface to accommodate various electrical components and connectivity to those components. The electrical interconnect device includes a plurality of intermittently spaced first pairs of upper and lower signal lines interwoven with a plurality of intermittently spaced second pairs of upper and lower signal lines. A bonding pad is arranged between adjacent upper and lower signal line pairs and can be connected thereto with conductive links placed upon the surface layer. Each bonding pad includes one or more pad vias which extend perpendicular to the upper surface to conductive structures arranged in lower layers. Approximately one-half of the array of bonding pads are connected to potential conductors. The pairs of upper signal lines can not only be linked, but also can be cut to form a more direct routing between target locations. Moreover, the upper and lower signal lines are connected in order for traces to extend across the entire interconnect structure for ease of testability.

Abstract translation: 提供了间隔地跨越衬底以形成互连装置或结构的电互连电池。 互连设备在上表面上是完全可定制的或可编程的，以适应各种电气部件和与这些部件的连接。 电互连装置包括多个间歇间隔的第一对上，下信号线，与多个间歇间隔的第二对上，下信号线交织。 接合焊盘布置在相邻的上部和下部信号线对之间，并且可以与放置在表面层上的导电连接件连接。 每个焊盘包括一个或多个衬垫通孔，其垂直于上表面延伸到布置在较低层中的导电结构。 大约一半的焊盘阵列连接到电位导体。 上层信号线对不仅可以链接，而且可以被切割，以在目标位置之间形成更直接的路由。 此外，上下信号线被连接以使得迹线在整个互连结构上延伸以便易于测试。

公开(公告)号：US5486427A

公开(公告)日：1996-01-23

申请号：US292890

申请日：1994-08-19

Applicant: David C. Koskenmaki ,  Clyde D. Calhoun

Inventor： David C. Koskenmaki ,  Clyde D. Calhoun

IPC: B23K35/02 ,  H01L21/52 ,  H01L21/60 ,  H01L23/498 ,  H05K3/10 ,  H05K3/32 ,  B22F1/00 ,  B22F9/00

CPC classification number: H01L24/83 ,  B23K35/0222 ,  H01L23/49883 ,  H01L24/29 ,  H05K3/323 ,  H01L2224/29298 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/12033 ,  H01L2924/14 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2203/0338 ,  H05K2203/0425 ,  H05K2203/128 ,  H05K3/102 ,  Y10T428/12 ,  Y10T428/12014

Abstract: The present invention provides a method for providing an array of metal microbeads on a substrate, preferably in a regular pattern of very fine, uniform size microspheres or microbeads at precise spacing or scale previously unachievable. The method of the present invention comprises the steps of providing a metal layer on a substrate that is partitioned into metal regions; heating the metal layer to a temperature sufficient to melt the metal and to permit beading of the layer into discrete microbeads.

Abstract translation: 本发明提供了一种用于在衬底上提供金属微珠阵列的方法，优选地以非常精细，均匀尺寸的微球或微珠的规则图案以精确的间隔或尺度提前预先不可实现。 本发明的方法包括在分隔成金属区域的基板上设置金属层的步骤; 将金属层加热到足以熔化金属的温度，并允许该层将珠粒串联成离散的微珠。