公开(公告)号：US10572222B2

公开(公告)日：2020-02-25

申请号：US16451759

申请日：2019-06-25

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/487 ,  G06F7/485

Abstract: Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.

公开(公告)号：US20200057610A1

公开(公告)日：2020-02-20

申请号：US16666066

申请日：2019-10-28

Applicant: Altera Corporation

Inventor： Benjamin Esposito

IPC: G06F7/57 ,  G06F15/78

Abstract: An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement amongst others multiplication, addition, sum-of-product, and multiply-accumulation operations in a first mode. In a second mode, the specialized processing blocks may operate as multiplexers and several specialized processing blocks may be cascaded to implement wider multiplexing functions. In a third mode, the specialized processing blocks may operate as register pipelines.

公开(公告)号：US20200050729A1

公开(公告)日：2020-02-13

申请号：US16549871

申请日：2019-08-23

Applicant: Altera Corporation

Inventor： Mark Stephen Wheeler ,  Gordon Raymond Chiu

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.

公开(公告)号：US10546087B1

公开(公告)日：2020-01-28

申请号：US15082870

申请日：2016-03-28

Applicant: Altera Corporation

Inventor： Sze Yin Lee ,  Arul Paniandi ,  Chong Tean Chuah ,  Siew Ling Yeoh ,  Yun Hui Moh

IPC: G06F17/50

Abstract: A method for generating configuration information using a computer aided design (CAD) tool includes a step to receive an intellectual property block. The method also includes a step to receive a configuration and status register (CSR) data file. The configuration and status register data file includes a user selected portion of runtime features from all of the available runtime features of the intellectual property block. The method may also include a step to receive an additional intellectual property block and an additional configuration and status register data file. Based on the two intellectual property blocks and the configuration and status register data files, a consolidated configuration and status register block may be formed. These intellectual property block(s) and configuration status register block(s) are formed on an integrated circuit device.

公开(公告)号：US20200026493A1

公开(公告)日：2020-01-23

申请号：US16586693

申请日：2019-09-27

Applicant: Altera Corporation

Inventor： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC: G06F7/483 ,  G06F7/487 ,  G06F7/485 ,  G06F7/499

Abstract: Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

公开(公告)号：US10474429B1

公开(公告)日：2019-11-12

申请号：US15331024

申请日：2016-10-21

Applicant: Altera Corporation

Inventor： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC: G06F7/483 ,  G06F7/485 ,  G06F7/487 ,  G06F7/499

Abstract: Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

公开(公告)号：US20190287638A1

公开(公告)日：2019-09-19

申请号：US16432638

申请日：2019-06-05

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C29/02 ,  G11C29/50 ,  H03K5/131 ,  H03K19/177

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US10409626B1

公开(公告)日：2019-09-10

申请号：US15287026

申请日：2016-10-06

Applicant: Altera Corporation

Inventor： Allen Chen ,  Abdel Rabi

IPC: G06F9/46 ,  G06F9/455

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. To help improve performance predictability, a hierarchical accelerator registry may be maintained on the coprocessor and/or on local servers. The accelerator registry may assign different classes and speed grades to various types of available resources to help the virtualized network better predict certain task latencies. The accelerator registry may be periodically updated based on changes detected in the local storage and hardware or based on changes detected in remote networks.

公开(公告)号：US20190273504A1

公开(公告)日：2019-09-05

申请号：US16414451

申请日：2019-05-16

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/093 ,  H03L7/099 ,  H03L7/089

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US10404627B2

公开(公告)日：2019-09-03

申请号：US15676402

申请日：2017-08-14

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  Vinson Chan ,  Divya Vijayaraghavan ,  Curt Wortman

IPC: H04L12/861 ,  H04L12/863

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.