公开(公告)号：US12164958B2

公开(公告)日：2024-12-10

申请号：US18132999

申请日：2023-04-11

Applicant: Imagination Technologies Limited

Inventor： Alistair Goudie ,  Panagiotis Velentzas

IPC: G06F9/48 ,  G06F12/0802

Abstract: Logic includes a task builder for building tasks comprising data items, a task scheduler for scheduling tasks for processing by a parallel processor, a data store arranged to map content of each data item to an item ID, and a linked-list RAM comprising an entry for each item ID. For each new data item, the task builder creates a new task by starting a new linked list, or adds the data item to an existing linked list. In each linked list, the entry for each data item records a pointer to a next item ID in the list. The task builder indicates when any of the tasks is ready for scheduling. The task scheduler identifies a ready task based on the indication from the task builder, and in response follows the pointers in the respective linked list in order to schedule the data items of the task for processing.

公开(公告)号：US20240402991A1

公开(公告)日：2024-12-05

申请号：US18799336

申请日：2024-08-09

Applicant: Imagination Technologies Limited

Inventor： Thomas Rose

IPC: G06F7/02 ,  G06F7/24 ,  G06F7/57 ,  G06F7/78

Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m−r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m−r−1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

公开(公告)号：US12159347B2

公开(公告)日：2024-12-03

申请号：US17852288

申请日：2022-06-28

Applicant: Imagination Technologies Limited

Inventor： Yoong Chert Foo ,  Salil Sahasrabudhe ,  Andrew Davy

IPC: G06T1/60 ,  G06T11/40 ,  G06T15/00 ,  G06T15/50 ,  G06T17/10

Abstract: A method and system for generating two or three dimensional computer graphics images using multisample antialiasing (MSAA) is provided, which enables memory bandwidth to be conserved. For each of one or more pixels it is determined whether all of a plurality of sample areas of that pixel are located within a particular primitive. For those pixels where it is determined that all the sample areas of that pixel are located within that primitive, a value is stored in a multisample memory for a smaller number of the sample areas of that pixel than the total number of the sample areas of that pixel and data is stored indicating that all the sample areas of that pixel are located within that primitive.

公开(公告)号：US12148093B2

公开(公告)日：2024-11-19

申请号：US17221005

申请日：2021-04-02

Applicant: Imagination Technologies Limited

Inventor： Jens Fursund ,  Luke T. Peterson

IPC: G06T15/80

Abstract: Rendering systems that can use combinations of rasterization rendering processes and ray tracing rendering processes are disclosed. In some implementations, these systems perform a rasterization pass to identify visible surfaces of pixels in an image. Some implementations may begin shading processes for visible surfaces, before the geometry is entirely processed, in which rays are emitted. Rays can be culled at various points during processing, based on determining whether the surface from which the ray was emitted is still visible. Rendering systems may implement rendering effects as disclosed.

公开(公告)号：US20240371077A1

公开(公告)日：2024-11-07

申请号：US18777462

申请日：2024-07-18

Applicant: Imagination Technologies Limited

Inventor： Gregory Clark ,  Steven J. Clohset ,  Luke T. Peterson

IPC: G06T15/06 ,  A63F13/52 ,  G06T7/13

Abstract: Ray tracing systems and computer-implemented methods are described for performing intersection testing on a bundle of rays with respect to a box. Silhouette edges of the box are identified from the perspective of the bundle of rays. For each of the identified silhouette edges, components of a vector providing a bound to the bundle of rays are obtained and it is determined whether the vector passes inside or outside of the silhouette edge. Results of determining, for each of the identified silhouette edges, whether the vector passes inside or outside of the silhouette edge, are used to determine an intersection testing result for the bundle of rays with respect to the box.

公开(公告)号：US12135886B2

公开(公告)日：2024-11-05

申请号：US18380608

申请日：2023-10-16

Applicant: Imagination Technologies Limited

Inventor： Ian King

IPC: G06F3/06

Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.

公开(公告)号：US12131564B2

公开(公告)日：2024-10-29

申请号：US17751518

申请日：2022-05-23

Applicant: Imagination Technologies Limited

Inventor： Timothy Smith

IPC: G06V10/46 ,  G06F18/22 ,  G06V10/426 ,  G06V10/44 ,  G06V10/52 ,  G06V30/24 ,  H04N19/117 ,  H04N19/132

CPC classification number: G06V30/2504 ,  G06F18/22 ,  G06V10/426 ,  G06V10/443 ,  G06V10/46 ,  G06V10/462 ,  G06V10/52 ,  H04N19/117 ,  H04N19/132 ,  G06T2207/20016 ,  G06V10/467

Abstract: A computer-implemented method for generating a feature descriptor for a location in an image for use in performing descriptor matching in analysing the image, the method comprising determining a set of samples characterising a location in an image by sampling scale-space data representative of the image, the scale-space data comprising data representative of the image at a plurality of length scales; and generating a feature descriptor in dependence on the determined set of samples.

公开(公告)号：US12131403B2

公开(公告)日：2024-10-29

申请号：US18231126

申请日：2023-08-07

Applicant: Imagination Technologies Limited

Inventor： Roger Hernando Buch ,  Panagiotis Velentzas ,  Richard Broadhurst ,  Xile Yang ,  John W. Howson

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06F12/02 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/52 ,  G06F12/0261 ,  G06T1/60

Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.

公开(公告)号：US20240354574A1

公开(公告)日：2024-10-24

申请号：US18589256

申请日：2024-02-27

Applicant: Imagination Technologies Limited

Inventor： Gunduz Vehbi Demirci ,  Cagatay Dikici

IPC: G06N3/082 ,  G06N3/063

CPC classification number: G06N3/082 ,  G06N3/063

Abstract: A neural network is compressed by selecting two or more adjacent layers, each having one or more input channels and one or more output channels, a first layer performing a first operation and a second layer performing a second operation. First and second matrices representative of sets of coefficients of the first and second layers are determined, having a plurality of elements representative of non-zero values and a plurality of elements representative of zero values. An array is formed comprising the first matrix and the second matrix by aligning the columns or rows of the first matrix that are representative of the output channels of the first layer with the columns or rows of the second matrix that are representative of the input channels of the second layer. The rows and/or columns of the array are rearranged into respective first and second sub-matrices. A compressed neural network is then outputted.

公开(公告)号：US20240346107A1

公开(公告)日：2024-10-17

申请号：US18617810

申请日：2024-03-27

Applicant: Imagination Technologies Limited

Inventor： Aria Ahmadi ,  Cagatay Dikici

IPC: G06F17/15 ,  G06F9/50

CPC classification number: G06F17/15 ,  G06F9/5027

Abstract: A method and data processing system for resampling a first set of samples using a neural network accelerator. The first set of samples is arranged in a tensor extending in at least a first dimension defined in a first coordinate system. A set of resampling parameters is determined, having a first resampling factor a_1/b_1 for a first dimension, and a first offset d_1 for the first dimension. At least a first number of kernels is obtained, and the first set of samples is resampled to produce a second set of samples, based on the first resampling factor and the first offset.