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公开(公告)号：US10338821B2
公开(公告)日：2019-07-02
申请号：US15285305
申请日：2016-10-04
Applicant: SMART Modular Technologies, Inc.
Inventor： Rajesh Ananthanarayanan , Jinying Shen , Amir Alavi
IPC: G06F3/06
Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information. The memory device with only one column in an embodiment does not require decoding of a column address. As such, the read latency of the memory device is significantly reduced.
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32.发明授权公开(公告)号：US09946469B2
公开(公告)日：2018-04-17
申请号：US15076433
申请日：2016-03-21
Applicant: SMART Modular Technologies, Inc.
Inventor： Fong-Long Lin , Shu-Cheng Lin
CPC classification number: G06F11/1044 , G11C16/0483 , G11C16/3427
Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.
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公开(公告)号：US09779016B1
公开(公告)日：2017-10-03
申请号：US13940118
申请日：2013-07-11
Applicant: SMART Modular Technologies, Inc.
Inventor： Jinying Shen , Robert Tower Frey , Kelvin Marino
CPC classification number: G06F12/0246 , G06F1/28 , G06F1/30 , G06F11/0754 , G06F11/1456 , G06F12/0868 , G06F2212/1016 , G06F2212/314
Abstract: An integrated circuit system, and a method of operation thereof, including: a memory unit having a volatile memory device with data and a non-volatile controller unit; a memory unit controller of the non-volatile controller unit for receiving a snoop signal for indicating an error; a non-volatile device of the memory unit for synchronously receiving data of the volatile memory device based on the snoop signal, the data autonomously copied without any intervention from outside the memory unit to prevent loss of the data; and an in-band command received by the memory unit, for autonomously restoring the data to the volatile memory device from the non-volatile device without any intervention from outside the memory unit.
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34.发明申请公开(公告)号：US20250103247A1
公开(公告)日：2025-03-27
申请号：US18373234
申请日：2023-09-26
Applicant: SMART Modular Technologies, Inc.
Inventor： Andrew Mills
IPC: G06F3/06
Abstract: Migrating data between byte-addressable and block-addressable storage devices in processor-based devices is disclosed. In this regard, a processor of a processor-based device is communicatively coupled to both a byte-addressable storage device and a block-addressable storage device. The processor is configured to present the byte-addressable storage device and the block-addressable storage device as a single virtual storage device (i.e., as either a byte-addressable virtual device or a block-addressable virtual storage device). The processor is further configured to identify a low-activity region in the byte-addressable storage device, and to also identify a high-activity region in the block-addressable storage device. The processor then exchanges a first storage region corresponding to the low-activity region and comprising a memory address region of the byte-addressable storage device with a second storage region corresponding to the high-activity region and comprising a block region of the block-addressable storage device.
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公开(公告)号：US20250077447A1
公开(公告)日：2025-03-06
申请号：US18238826
申请日：2023-08-28
Applicant: SMART Modular Technologies, Inc.
Inventor： Torry Steed , Andrew Mills
Abstract: Systems and methods for balancing memory speeds are disclosed. In particular, at start up, a host to memory bus speed is determined and compared to a default internal memory device bus speed. A memory device control circuit may then determine if an internal bus should be overclocked or slowed down to match the host to memory bus speed. The selection may then be stored in a register and made available to a host memory controller (e.g., through polling or the like). Selection of an internal speed may also be based on other factors such as power savings or the like. In either event, having the flexibility to set the internal speed based on one or more such criteria may result in improved efficiency.
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Patent Agency Ranking
公开(公告)号：US20250076939A1
公开(公告)日：2025-03-06
申请号：US18240402
申请日：2023-08-31
Applicant: SMART Modular Technologies, Inc.
Inventor： Satyanarayan Iyer , Torry Steed , Luis Fukazawa
Abstract: Memory modules comprise memory chips coupled to a surface of one or more substrates. The memory chips contain large numbers of storage cells that consume power during normal operation, generating heat in the memory chips and causing temperatures to increase. As the temperatures increase, leakage currents can increase in the memory chips, and performance of the memory chips can decrease. A memory module includes memory chips disposed on a substrate and an active cooling device disposed on the substrate to increase the rate at which heat is dissipated to reduce or maintain temperatures and thereby save power and improve performance. In some examples, the active cooling device is disposed on a side of a memory chip opposite to the card in the memory module to improve cooling of the memory chips. In some examples, the active cooling device is a thermoelectric device.
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公开(公告)号：US20230305922A1
公开(公告)日：2023-09-28
申请号：US17703362
申请日：2022-03-24
Applicant: SMART Modular Technologies, Inc.
Inventor： Robert Tower Frey , Kelvin Marino
CPC classification number: G06F11/1068 , G06F1/30 , G06F11/0772 , G06F11/0793 , G06F13/4282
Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system including: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device with data, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.
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公开(公告)号：US10510432B1
公开(公告)日：2019-12-17
申请号：US15659420
申请日：2017-07-25
Applicant: SMART Modular Technologies, Inc.
Inventor： Jinying Shen
Abstract: Approaches, techniques, and mechanisms are disclosed for a test adapter designed to improve testability of non-volatile dual in-line memory modules (NVDIMM) on automatic test equipment (ATE) testers or in-system boards, which have inadequate power supplies. An NVDIMM includes both volatile memories and non-volatile memories. A test adapter is designed to supply increased power to an NVDIMM. A test adapter is implemented using an interposer or a printed circuit board (PCB) that may be inserted into a socket on an ATE tester or on an end-user system-level board. The interposer or PCB includes a power socket for attaching a power cable to supply the external power supply to the NVDIMM. A power on/off sequence is controlled by an ATE tester to simulate or test a system power on/off sequence. An external input power is always on, but both serial and backup power signals are only on during tests of an NVDIMM.
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公开(公告)号：US10185609B2
公开(公告)日：2019-01-22
申请号：US15388704
申请日：2016-12-22
Applicant: SMART Modular Technologies, Inc.
Inventor： Shu-Cheng Lin
Abstract: Approaches, techniques, and mechanisms are disclosed for improving data retention using a virtual timer. A memory controller may use a raw bit error rate (RBER) to find an equivalent temperature-accelerated data age of a data item. The data age is computed by using the initial RBER of virtual timing data (VTD) as a virtual write in time of the data item compared to a present time using the current RBER of the VTD. When the data age is determined to exceed a data retention threshold, a data refresh is performed on the data item at the memory block on the memory device. The data age may be stored as virtual timing data on the memory block.
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40.发明申请公开(公告)号：US20180232159A1
公开(公告)日：2018-08-16
申请号：US15955566
申请日：2018-04-17
Applicant: SMART Modular Technologies, Inc.
Inventor： Fong-Long Lin , Shu-Cheng Lin
CPC classification number: G06F11/1044 , G11C16/0483 , G11C16/3427
Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.
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