公开(公告)号：US20170207162A1

公开(公告)日：2017-07-20

申请号：US15477853

申请日：2017-04-03

Applicant: Amkor Technology, Inc.

Inventor： Seung Woo Lee ,  Byong Jin Kim ,  Won Bae Bang ,  Sang Goo Kang

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49861 ,  H01L21/4839 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

公开(公告)号：US09704747B2

公开(公告)日：2017-07-11

申请号：US14218292

申请日：2014-03-18

Applicant: Amkor Technology, Inc.

Inventor： Ji Yeon Ryu ,  Byong Jin Kim ,  Jae Beum Shim

IPC: H01L23/48 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L21/78 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Provided are a semiconductor device having a stably formed structure capable of being electrically connected to a second electronic device without causing damage to the semiconductor device, and a manufacturing method thereof. In one embodiment, the semiconductor device may comprise a semiconductor die, an encapsulation part formed on lateral surfaces of the semiconductor die, a dielectric layer formed on the semiconductor die and the encapsulation part, a redistribution layer passing through a part of the dielectric layer and electrically connected to the semiconductor die, a plurality of conductive balls extending through other parts of the dielectric layer and electrically connected to the redistribution layer where the conductive balls are exposed to an environment outside of the semiconductor device, and conductive vias extending through the encapsulation part and electrically connected to the redistribution layer.

公开(公告)号：US09653336B2

公开(公告)日：2017-05-16

申请号：US15073219

申请日：2016-03-17

Applicant: Amkor Technology, Inc.

Inventor： Yi Seul Han ,  Jae Beum Shim ,  Byong Jin Kim ,  In Bae Park

IPC: H01L21/44 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/288 ,  H01L23/31

CPC classification number: H01L21/6836 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11009 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/1329 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/136 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/0231

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

公开(公告)号：US20160211221A1

公开(公告)日：2016-07-21

申请号：US14995806

申请日：2016-01-14

Applicant: Amkor Technology, Inc.

Inventor： Jin Young Kim ,  Keun Soo Kim ,  Byong Jin Kim ,  Jae Yoon Kim ,  Do Hyun Na ,  Hyun Il Moon ,  Dae Byong Kang

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49861 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/83005

Abstract: A selectively shielded and/or three-dimensional semiconductor device and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor device that comprises a composite plate for selective shielding and/or a three-dimensional embedded component configuration.

Abstract translation: 选择性屏蔽和/或三维半导体器件及其制造方法。 例如但不限于，本公开的各个方面提供了一种半导体器件，其包括用于选择性屏蔽的复合板和/或三维嵌入式部件配置。

公开(公告)号：US20160027753A1

公开(公告)日：2016-01-28

申请号：US14593310

申请日：2015-01-09

Applicant: Amkor Technology, Inc.

Inventor： Hyung Il Jeon ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Min Bae ,  Tae Ki Kim

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L21/78 ,  H01L21/48 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/18161 ,  H01L2224/81

Abstract: In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

Abstract translation: 在一个实施例中，半导体器件包括在绝缘层的第一表面上具有绝缘层和导电图案的单层衬底。 半导体管芯安装在单层衬底的第一表面上并电连接到导电图案。 导电凸块也在单层基板的第一表面上并且通过导电图案电连接到半导体管芯。 密封剂与单层基材的第一表面的至少部分重叠。 导电凸块至少部分地暴露在密封剂中。

公开(公告)号：US20150279767A1

公开(公告)日：2015-10-01

申请号：US14722110

申请日：2015-05-26

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Kyung Su Kim ,  Hyung Il Jeon ,  Jae Doo Kwon

IPC: H01L23/495 ,  H01L23/043 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/50 ,  H01L23/043 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip.

Abstract translation: 在一个实施例中，引线框架封装结构包括引线框架，引线框架具有围绕管芯焊盘的侧面并且在其上形成有多个引线。 将电子芯片安装在芯片上，并且将壳体附接到引线框架以密封引线和电子芯片。 一个或多个排出孔形成在一个或多个特定的引线上并且延伸穿过一个或多个特定的引线和/或延伸穿过管芯的预定位置。 排出孔被构造成排出在组装过程中形成的空气压力，从而提高封装的电子芯片的可靠性。

公开(公告)号：US09129975B2

公开(公告)日：2015-09-08

申请号：US13750022

申请日：2013-01-25

Applicant: Amkor Technology, Inc.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Gi Jeong Kim

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L29/06 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/495 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure.

Abstract translation: 在一个实施例中，一种用于形成电子封装结构的方法包括提供在第一或顶表面上具有第一端子的单个单元引线框架。 电子设备连接到单个单元引线框架并电连接到第一端子。 引线框，第一端子和电子器件用封装材料封装。 然后通过去除引线框架的第二或下表面的部分来形成第二端子。 在一个实施例中，该方法可用于制造薄的衬底芯片级封装（“tsCSP”）型结构。

公开(公告)号：US20150130054A1

公开(公告)日：2015-05-14

申请号：US14538018

申请日：2014-11-11

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Jae Ung Lee ,  Byong Jin Kim ,  Yoon Ki Namkung ,  Se Man Oh

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/16 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A semiconductor package and a method for manufacturing a semiconductor package that comprises a unit substrate, for example to which a semiconductor chip is attached, embedded in a base substrate on which a semiconductor device may be mounted. The base substrate may, for example, comprise vias between top and bottom surfaces thereof and/or vias between the top surface of the base substrate and a top surface of the unit substrate embedded within the base substrate.

Abstract translation: 一种半导体封装件和一种半导体封装件的制造方法，该半导体封装件包括单元衬底，例如安装有半导体芯片的单元衬底，该半导体封装件埋设在可安装半导体器件的基底衬底中。 基底可以例如在其顶表面和底表面之间包括通孔和/或基底基底的顶表面之间的通孔和嵌入基底衬底内的单元基底的顶表面。

公开(公告)号：US20130277815A1

公开(公告)日：2013-10-24

申请号：US13750022

申请日：2013-01-25

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Gi Jeong Kim

IPC: H01L21/56 ,  H01L23/495

CPC classification number: H01L23/49541 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/495 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure.

Abstract translation: 在一个实施例中，一种用于形成电子封装结构的方法包括提供在第一或顶表面上具有第一端子的单个单元引线框架。 电子设备连接到单个单元引线框架并电连接到第一端子。 引线框，第一端子和电子器件用封装材料封装。 然后通过去除引线框架的第二或下表面的部分来形成第二端子。 在一个实施例中，该方法可用于制造薄的衬底芯片级封装（“tsCSP”）型结构。

公开(公告)号：US10468343B2

公开(公告)日：2019-11-05

申请号：US15874602

申请日：2018-01-18

Applicant: Amkor Technology, Inc.

Inventor： Seung Woo Lee ,  Byong Jin Kim ,  Won Bae Bang ,  Sang Goo Kang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.