公开(公告)号：US10403599B2

公开(公告)日：2019-09-03

申请号：US15499557

申请日：2017-04-27

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba

IPC: H01L25/16 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498

Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide improved signal transmission of 1-2 GHz up to 20-60 GHz bandwidth for each 15 mm length, for example. The embedded organic interposers are not limited to use with memory modules.

公开(公告)号：US09935075B2

公开(公告)日：2018-04-03

申请号：US15237936

申请日：2016-08-16

Applicant: Invensas Corporation

Inventor： Shaowu Huang ,  Javier A. Delacruz

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/49 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/85 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/49171 ,  H01L2224/49179 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

公开(公告)号：US20170141020A1

公开(公告)日：2017-05-18

申请号：US15086899

申请日：2016-03-31

Applicant: Invensas Corporation

Inventor： Grant Villavicencio ,  Sangil Lee ,  Roseann Alatorre ,  Javier A. Delacruz ,  Scott McGrath

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/56 ,  H01L23/053 ,  H01L21/48 ,  H01L23/31 ,  H01L23/043

CPC classification number: H01L23/49811 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/043 ,  H01L23/053 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15333 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

公开(公告)号：US11270979B2

公开(公告)日：2022-03-08

申请号：US16842199

申请日：2020-04-07

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L25/065 ,  G06F15/78 ,  H01L25/18 ,  H01L23/00 ,  H01L23/532 ,  G06F15/76

Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

公开(公告)号：US20200227360A1

公开(公告)日：2020-07-16

申请号：US16833445

申请日：2020-03-27

Applicant: Invensas Corporation

Inventor： Shaowu Huang ,  Javier A. Delacruz

IPC: H01L23/552

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

公开(公告)号：US10483217B2

公开(公告)日：2019-11-19

申请号：US15977905

申请日：2018-05-11

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Sangil Lee ,  Craig Mitchell ,  Gabriel Z. Guevara ,  Javier A. Delacruz

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  B23K1/00 ,  H01L23/538 ,  H01L23/31

Abstract: Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.

公开(公告)号：US10149377B2

公开(公告)日：2018-12-04

申请号：US15192549

申请日：2016-06-24

Applicant: Invensas Corporation

Inventor： Shaowu Huang ,  Javier A. Delacruz ,  Belgacem Haba

IPC: H05K1/02 ,  H05K3/10 ,  H05K1/18 ,  H05K1/11 ,  H03H7/38 ,  H01P11/00 ,  H01L21/48 ,  H01P3/08 ,  H01L23/498 ,  H01L23/66 ,  H01P5/02 ,  H01P3/02 ,  H01P3/18

Abstract: A stacked, multi-layer transmission line is provided. The stacked transmission line includes at least a pair of conductive traces, each conductive trace having a plurality of conductive stubs electrically coupled thereto. The stubs are disposed in one or more separate spatial layers from the conductive traces.

公开(公告)号：US20180114747A1

公开(公告)日：2018-04-26

申请号：US15334606

申请日：2016-10-26

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Wael Zohni ,  Liang Wang ,  Akash Agrawal

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/562

Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

公开(公告)号：US20180040572A1

公开(公告)日：2018-02-08

申请号：US15670382

申请日：2017-08-07

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Sangil Lee ,  Craig Mitchell ,  Gabriel Z. Guevara ,  Javier A. Delacruz

IPC: H01L23/00 ,  H01L23/498 ,  B23K1/00 ,  H01L21/48

CPC classification number: H01L23/562 ,  B23K1/0008 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.

公开(公告)号：US20180040544A1

公开(公告)日：2018-02-08

申请号：US15660718

申请日：2017-07-26

Applicant: Invensas Corporation

Inventor： Rajesh Emeka Katkar ,  Min Tao ,  Javier A. Delacruz ,  Hoki Kim ,  Akash Agrawal

IPC: H01L23/498 ,  H05K3/34 ,  H05K1/18 ,  H05K1/11 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L23/49805 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49833 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48105 ,  H01L2224/48225 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/15159 ,  H01L2924/15162 ,  H01L2924/15172 ,  H01L2924/15331 ,  H01L2924/15333 ,  H05K1/117 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3405 ,  H05K3/366 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/09845 ,  H05K2201/10159 ,  H05K2201/10522

Abstract: Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.