公开(公告)号：US10243576B2

公开(公告)日：2019-03-26

申请号：US15974756

申请日：2018-05-09

Applicant: Maxlinear, Inc.

Inventor： Eric Fogleman ,  Sheng Ye ,  Xuefeng Chen ,  Kok Lim Chan

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/46 ,  H03M1/12

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

公开(公告)号：US20190044525A1

公开(公告)日：2019-02-07

申请号：US16154167

申请日：2018-10-08

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Gallagher

IPC: H03M1/06 ,  H04L7/00 ,  H04L25/08 ,  H03M1/10 ,  H03M1/50 ,  H04W56/00 ,  H03M1/12

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

公开(公告)号：US20180262201A1

公开(公告)日：2018-09-13

申请号：US15974756

申请日：2018-05-09

Applicant: Maxlinear, Inc.

Inventor： Eric Fogleman ,  Sheng Ye ,  Xuefeng Chen ,  Kok Lim Chan

IPC: H03M1/06 ,  H03M1/00

CPC classification number: H03M1/0617 ,  H03M1/001 ,  H03M1/069 ,  H03M1/125 ,  H03M1/46 ,  H03M1/462

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

公开(公告)号：US09813052B2

公开(公告)日：2017-11-07

申请号：US15444662

申请日：2017-02-28

Applicant: Maxlinear, Inc.

Inventor： Yongjian Tang ,  Xuefeng Chen

IPC: H03K17/16 ,  H03K17/06

CPC classification number: H03K17/063 ,  H03K17/687 ,  H03K2217/0054

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

公开(公告)号：US09800253B2

公开(公告)日：2017-10-24

申请号：US15230735

申请日：2016-08-08

Applicant: MaxLinear, Inc.

Inventor： Eric Fogleman ,  Sheng Ye ,  Xuefeng Chen ,  Kok Lim Chan

IPC: H03M1/00 ,  H03M1/06

CPC classification number: H03M1/0617 ,  H03M1/001 ,  H03M1/069 ,  H03M1/125 ,  H03M1/46 ,  H03M1/462

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

公开(公告)号：US09584112B2

公开(公告)日：2017-02-28

申请号：US14585707

申请日：2014-12-30

Applicant: Maxlinear, Inc.

Inventor： Yongjian Tang ,  Xuefeng Chen

IPC: H03K17/16 ,  H03K17/687 ,  H03K17/06

CPC classification number: H03K17/063 ,  H03K17/687 ,  H03K2217/0054

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor. The pull-down path includes a diode-connected MOS transistor coupled in parallel with a second MOS transistor that couples the gate terminal of the switching MOS transistor to ground via third and fourth MOS transistors when the switching MOS transistor is in an OFF state. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage, VDD, to activate the pull-down path. A capacitor may be coupled between gate and source terminals of the switching MOS transistor to switch the switching MOS transistor to an ON state.

Abstract translation: 用于可靠自举开关的方法和系统可以包括用自举开关对接收到的信号进行采样，其中自举开关包括具有耦合到开关MOS晶体管的栅极端子的下拉通路的开关金属氧化物半导体（MOS）晶体管。 下拉路径包括与第二MOS晶体管并联耦合的二极管连接的MOS晶体管，当开关MOS晶体管处于截止状态时，第二MOS晶体管通过第三和第四MOS晶体管将开关MOS晶体管的栅极端子接地。 第三和第四MOS晶体管可以与第二MOS晶体管串联。 第四晶体管的栅极端子可以从地切换到电源电压VDD，以激活下拉路径。 电容器可以耦合在开关MOS晶体管的栅极和源极端子之间，以将开关MOS晶体管切换到导通状态。

公开(公告)号：US09337859B2

公开(公告)日：2016-05-10

申请号：US14812327

申请日：2015-07-29

Applicant: MaxLinear, Inc.

Inventor： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

Abstract: Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.

Abstract translation: 提供了用于控制信号处理输出的方法和系统。 在信号处理电路中，通过多个量化级别搜索与模拟输入匹配的量化级别，以及当在特定时间量内搜索失败时，调整信号处理电路的输出的至少一部分。 调整包括将输出的至少部分设置为预定值。 设置输出或其部分可以包括在正常处理路径的输出和被配置用于处理搜索失败的代码生成路径的输出之间进行选择。 可以产生用于控制信号处理电路的输出的产生的定时信息。 定时信息可以用于在通过多个量化级别的搜索期间测量每周期操作时间。

公开(公告)号：US20150381196A1

公开(公告)日：2015-12-31

申请号：US14843445

申请日：2015-09-02

Applicant: MaxLinear, Inc.

Inventor： Eric Fogleman ,  Sheng Ye ,  Xuefeng Chen ,  Kok Lim Chan

IPC: H03M1/46 ,  H03M1/12

CPC classification number: H03M1/0617 ,  H03M1/001 ,  H03M1/069 ,  H03M1/125 ,  H03M1/46 ,  H03M1/462

Abstract: Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits.

Abstract translation: 提供了利用抢占位设置决定的异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统。 特别地，这样的SAR ADC可以可操作用于当发生针对每个比较步骤确定有效输出判定的故障时，将一个或多个剩余的比特设置在对应于...的码字中但不包括一个或多个重叠的冗余比特 比较步骤，到一个特定的价值。 该值可以从紧接在前的判定中确定的比特的值导出。 可以基于动态和/或适应性标准来确定故障。 可以设置标准，例如，以便确保SAR ADC的模拟输入电压与其中使用的数模转换器（DAC）的模拟输出电压之间的差异幅度在电压的重叠范围内 对应于重叠的冗余位。

公开(公告)号：US20150162928A1

公开(公告)日：2015-06-11

申请号：US14585656

申请日：2014-12-30

Applicant: MaxLinear, Inc.

Inventor： Eric Fogleman ,  Sheng Ye ,  Xuefeng Chen ,  Kok Lim Chan

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/0617 ,  H03M1/001 ,  H03M1/069 ,  H03M1/125 ,  H03M1/46 ,  H03M1/462

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中先占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。

公开(公告)号：US20150124915A1

公开(公告)日：2015-05-07

申请号：US14590250

申请日：2015-01-06

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumer ,  Sheng Ye ,  Timothy Leo Gallagher

IPC: H03M1/06 ,  H04L7/00 ,  H03M1/12 ,  H04L25/08

CPC classification number: H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。