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31.发明授权Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) 有权用于异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统公开(公告)号：US08922415B2
公开(公告)日：2014-12-30
申请号：US13964043
申请日：2013-08-10
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中抢占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。
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32.发明申请METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) 有权非线性随机逼近寄存器（SAR）模数转换器（ADCS）的方法与系统公开(公告)号：US20140043175A1
公开(公告)日：2014-02-13
申请号：US13964043
申请日：2013-08-10
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
IPC: H03M1/46
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中抢占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。
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公开(公告)号：US10404304B2
公开(公告)日：2019-09-03
申请号：US16110571
申请日：2018-08-23
Applicant: Maxlinear, Inc.
Inventor： Raja Pullela , Sheng Ye , Morten Damgaard
IPC: H04B1/18
Abstract: Methods and systems for a baseband cross-bar may comprise receiving one or more radio frequency (RF) signals in a wireless communication device via antennas coupled to a plurality of receiver paths in the wireless device. The received RF signals may be converted to baseband frequencies. One or more of the down-converted signals may be coupled to receiver paths utilizing a baseband cross-bar. The baseband cross-bar may comprise a plurality of switches, which may comprise CMOS transistors. In-phase and quadrature signals may be processed in the one or more of the plurality of receiver paths. The one or more RF signals comprise cellular signals and/or global navigation satellite signals. A single-ended received RF signal may be converted to a differential signal in one or more of the plurality of receiver paths. The baseband cross-bar may be controlled utilizing a reduced instruction set computing (RISC) processor.
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公开(公告)号：US10404260B2
公开(公告)日：2019-09-03
申请号：US15906578
申请日：2018-02-27
Applicant: Maxlinear, Inc.
Inventor： Sangeetha Gopalakrishnan , Sheng Ye , Vamsi Paidi , Raghava Manas Bachu
Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.
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公开(公告)号：US10256827B2
公开(公告)日：2019-04-09
申请号：US15837312
申请日：2017-12-11
Applicant: Maxlinear, Inc.
Inventor： Sheng Ye
Abstract: A phase locked loop may be operable to generate, utilizing a frequency multiplier, a reference clock signal whose frequency is an integer M times a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.
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Patent Agency Ranking
公开(公告)号：US10211868B2
公开(公告)日：2019-02-19
申请号：US14918793
申请日：2015-10-21
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Sheng Ye
Abstract: A transceiver comprises local oscillator circuitry, phase noise determination circuitry, mixing circuitry, and digital signal processing circuitry. The local oscillator circuitry is operable to generate a local oscillator signal. The phase noise determination circuitry is operable to introduce a frequency-dependent phase shift to the local oscillator signal to generate a phase-shifted version of the local oscillator signal. The mixing circuitry is operable to mix the local oscillator signal and the phase-shifted version of the local oscillator to generate a baseband signal having an amplitude proportional to a phase difference between the local oscillator signal and the phase-shifted version of the local oscillator signal. The digital signal processing circuitry is operable to process the baseband signal to determine a phase error of the local oscillator signal, and perform signal compensation based on the determined phase error.
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公开(公告)号：US20180367178A1
公开(公告)日：2018-12-20
申请号：US16110571
申请日：2018-08-23
Applicant: Maxlinear, Inc.
Inventor： Raja Pullela , Sheng Ye , Morten Damgaard
IPC: H04B1/18
CPC classification number: H04B1/18
Abstract: Methods and systems for a baseband cross-bar may comprise receiving one or more radio frequency (RF) signals in a wireless communication device via antennas coupled to a plurality of receiver paths in the wireless device. The received RF signals may be converted to baseband frequencies. One or more of the down-converted signals may be coupled to receiver paths utilizing a baseband cross-bar. The baseband cross-bar may comprise a plurality of switches, which may comprise CMOS transistors. In-phase and quadrature signals may be processed in the one or more of the plurality of receiver paths. The one or more RF signals comprise cellular signals and/or global navigation satellite signals. A single-ended received RF signal may be converted to a differential signal in one or more of the plurality of receiver paths. The baseband cross-bar may be controlled utilizing a reduced instruction set computing (RISC) processor.
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公开(公告)号：US10148417B2
公开(公告)日：2018-12-04
申请号：US15185429
申请日：2016-06-17
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Sheng Ye
Abstract: A method and system for duty-cycled high speed clock and data recovery with forward error correction are provided. The system operates on a first digital signal comprising a first plurality of samples and a second digital signal comprising a second plurality of samples. The second plurality of samples may be a subset of the first plurality of samples, for example, if the first and second pluralities of samples are generated by one analog-to-digital converter. A clock and data recovery module is operable to produce a timing indication according the second digital signal. The second plurality of samples is sampled intermittently. The discontinuity between bursts of samples in the second signal corresponds to a duty cycle. A forward error correction module is operable to produce a digital error-corrected signal according to the first digital signal and the timing indication.
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公开(公告)号：US10063906B2
公开(公告)日：2018-08-28
申请号：US15426382
申请日：2017-02-07
Applicant: Maxlinear, Inc.
Inventor： Anand Anandakumar , Sheng Ye , Curtis Ling
IPC: G06F3/00 , H03K9/00 , H04N21/426 , H04N21/443 , H04N21/61 , H04N21/438
CPC classification number: H04N21/4263 , H04N5/44 , H04N5/50 , H04N21/4383 , H04N21/4436 , H04N21/4622 , H04N21/6143
Abstract: Methods and systems for multi-path video and network channels may comprise a communication device comprising a wideband tuner (WB) and a narrowband tuner (NB). A video channel and a network channel may be received in the WB when the device is operating in a first stage. A video channel and a network channel may be received in the WB and the network channel may also be received in the NB when the device is operating in a second stage. The network channel may be received in the NB when the device is operating in a third stage. The reception of the network channel from both the WB and NB may enable a continuous reception of the network channel in a transition between the first and third stages. The WB may be operable to receive a plurality of channels and the NB may be operable to receive a single channel.
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40.发明申请公开(公告)号：US20180013442A1
公开(公告)日：2018-01-11
申请号：US15711177
申请日：2017-09-21
Applicant: Maxlinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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