公开(公告)号：US20210225932A1

公开(公告)日：2021-07-22

申请号：US17223024

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H01L27/22 ,  H01L43/12 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

公开(公告)号：US20210119115A1

公开(公告)日：2021-04-22

申请号：US17134460

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US20210005662A1

公开(公告)日：2021-01-07

申请号：US16531108

申请日：2019-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

公开(公告)号：US09972498B2

公开(公告)日：2018-05-15

申请号：US15081932

申请日：2016-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Chih-Hsun Lin ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Po-Cheng Huang ,  Kun-Ju Li ,  Wen-Chin Lin

IPC: B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/28247 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/31053 ,  H01L21/31056 ,  H01L29/66545

Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

公开(公告)号：US09887158B1

公开(公告)日：2018-02-06

申请号：US15340982

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC: H01L23/52 ,  H01L29/41 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/41758 ,  H01L29/66628 ,  H01L29/7833

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.

公开(公告)号：US20180012771A1

公开(公告)日：2018-01-11

申请号：US15678117

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US09773682B1

公开(公告)日：2017-09-26

申请号：US15201628

申请日：2016-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US20170162396A1

公开(公告)日：2017-06-08

申请号：US15081932

申请日：2016-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Chih-Hsun Lin ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Po-Cheng Huang ,  Kun-Ju Li ,  Wen-Chin Lin

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/28247 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/31053 ,  H01L21/31056 ,  H01L29/66545

Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

公开(公告)号：US20160336269A1

公开(公告)日：2016-11-17

申请号：US14709500

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Shu Min Huang ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Pei-Yu Lee ,  Min-Chuan Tsai ,  Chih-Hsun Lin ,  Wu-Sian Sie ,  Jen-Chieh Lin

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor process includes the following steps. A dielectric layer having a recess is formed on a substrate. A barrier layer is formed to cover the recess, thereby the barrier layer having two sidewall parts. A conductive layer is formed on the barrier layer by an atomic layer deposition process, thereby the conductive layer having two sidewall parts. The two sidewall parts of the conductive layer are pulled down. A conductive material fills the recess and has a part contacting the two sidewall parts of the barrier layer protruding from the two sidewall parts of the conductive layer, wherein the equilibrium potential difference between the barrier layer and the conductive layer is different from the equilibrium potential difference between the barrier layer and the conductive material. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成阻挡层以覆盖凹部，由此阻挡层具有两个侧壁部分。 通过原子层沉积工艺在阻挡层上形成导电层，由此导电层具有两个侧壁部分。 导电层的两个侧壁部分被拉下。 导电材料填充凹部，并且具有接触从导电层的两个侧壁部分突出的阻挡层的两个侧壁部分的部分，其中阻挡层和导电层之间的平衡电位差不同于平衡电位差 在阻挡层和导电材料之间。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20160148816A1

公开(公告)日：2016-05-26

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成第一材料层; 在所述第一材料层上形成停止层; 在所述停止层上形成第二材料层; 并且进行平面化处理以去除第二材料层，停止层以及用于形成栅极层的第一材料层的一部分。