公开(公告)号：US08423724B2

公开(公告)日：2013-04-16

申请号：US12878008

申请日：2010-09-08

Applicant: Kelvin Marino ,  Michael Rubino ,  Mike H. Amidi

Inventor： Kelvin Marino ,  Michael Rubino ,  Mike H. Amidi

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F11/1441

Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.

Abstract translation: 一种用于操作动态备份存储系统的方法包括：提供包括第一等级存储器设备和随后的存储器设备的高速存储器; 提供用于从高速存储器保存数据的非易失性存储器; 以及提供控制逻辑单元，用于控制来自所述高速存储器的执行程序的中央处理单元的访问，所述高速存储器包括当所述中央处理单元从所述第一等级存储器设备执行所述程序时恢复所述后续行列。

公开(公告)号：US08379391B2

公开(公告)日：2013-02-19

申请号：US12465560

申请日：2009-05-13

Applicant: Mike H. Amidi ,  Robert S. Pauley ,  Satyanarayan Shivkumar Iyer

Inventor： Mike H. Amidi ,  Robert S. Pauley ,  Satyanarayan Shivkumar Iyer

IPC: H05K5/00 ,  H05K7/00

CPC classification number: H05K1/141 ,  G11C5/04 ,  H01L25/0652 ,  H01L2924/0002 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A memory module with attached transposer and interposers to provide additional surface area for the placement of memory devices is disclosed. The memory module includes a memory board with a first surface, a second surface and an edge with a set of electrical contacts. A transposer is attached to each surface of the memory board, and an interposer is attached to each transposer on the opposite surface of the transposer from the memory board. The interposer has space to allow placement of memory devices on both a first surface between the interposer and the memory board, and on a second surface of the interposer away from the memory board.

Abstract translation: 公开了一种具有连接的转印器和插入件以提供用于存储器件的放置的附加表面积的存储器模块。 存储器模块包括具有第一表面，第二表面和具有一组电触点的边缘的存储器板。 将转移器连接到存储器板的每个表面，并且插入器附接到转移器的与存储器板相反的表面上的每个转台。 插入器具有允许将存储器件放置在插入器和存储器板之间的第一表面上以及在插入器的远离存储器板的第二表面上的空间。

公开(公告)号：US07724604B2

公开(公告)日：2010-05-25

申请号：US11552949

申请日：2006-10-25

Applicant: Mike H. Amidi ,  Satyadev Kolli

Inventor： Mike H. Amidi ,  Satyadev Kolli

IPC: G11C5/14

CPC classification number: G11C5/143 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2211/4067

Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

Abstract translation: 提供了一种用于存储器模块的时钟和电源故障检测的系统，方法和装置。 在一个实施例中，提供了一种系统。 该系统包括电压检测电路和时钟检测电路。 该系统还包括耦合到电压检测电路和时钟检测电路的控制器。 该系统还包括耦合到控制器的存储器控​​制状态机。 该系统包括耦合到存储器控制状态机的易失性存储器。 该系统还包括耦合到控制器和存储器控制状态机的电池和电池调节电路。 电池，电池调节电路，易失性存储器，存储器控制状态机，控制器，时钟检测电路和电压检测电路都集成在一体式存储器模块中。

公开(公告)号：US20060117152A1

公开(公告)日：2006-06-01

申请号：US10752151

申请日：2004-01-05

Applicant: Hossein Amidi ,  Kelvin Marino ,  Satyadey Kolli

Inventor： Hossein Amidi ,  Kelvin Marino ,  Satyadey Kolli

IPC: G06F13/00

CPC classification number: G11C8/12 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

Abstract translation: 透明的四级存储器模块具有前侧和后侧。 前侧具有堆叠在第一存储器等级上的第三存储器级。 背面具有堆叠在第二存储器等级上的第四存储器级。 耦合到存储器模块的仿真器基于从存储器控制器接收的信号来激活并控制来自第一存储器级，第二存储器级，第三存储器级或第四存储器级的一个单独的存储器级。

公开(公告)号：US20250103247A1

公开(公告)日：2025-03-27

申请号：US18373234

申请日：2023-09-26

Applicant: SMART Modular Technologies, Inc.

Inventor： Andrew Mills

IPC: G06F3/06

Abstract: Migrating data between byte-addressable and block-addressable storage devices in processor-based devices is disclosed. In this regard, a processor of a processor-based device is communicatively coupled to both a byte-addressable storage device and a block-addressable storage device. The processor is configured to present the byte-addressable storage device and the block-addressable storage device as a single virtual storage device (i.e., as either a byte-addressable virtual device or a block-addressable virtual storage device). The processor is further configured to identify a low-activity region in the byte-addressable storage device, and to also identify a high-activity region in the block-addressable storage device. The processor then exchanges a first storage region corresponding to the low-activity region and comprising a memory address region of the byte-addressable storage device with a second storage region corresponding to the high-activity region and comprising a block region of the block-addressable storage device.

公开(公告)号：US20250077447A1

公开(公告)日：2025-03-06

申请号：US18238826

申请日：2023-08-28

Applicant: SMART Modular Technologies, Inc.

Inventor： Torry Steed ,  Andrew Mills

IPC: G06F13/16 ,  G06F13/22 ,  G06F13/42

Abstract: Systems and methods for balancing memory speeds are disclosed. In particular, at start up, a host to memory bus speed is determined and compared to a default internal memory device bus speed. A memory device control circuit may then determine if an internal bus should be overclocked or slowed down to match the host to memory bus speed. The selection may then be stored in a register and made available to a host memory controller (e.g., through polling or the like). Selection of an internal speed may also be based on other factors such as power savings or the like. In either event, having the flexibility to set the internal speed based on one or more such criteria may result in improved efficiency.

公开(公告)号：US20250076939A1

公开(公告)日：2025-03-06

申请号：US18240402

申请日：2023-08-31

Applicant: SMART Modular Technologies, Inc.

Inventor： Satyanarayan Iyer ,  Torry Steed ,  Luis Fukazawa

IPC: G06F1/20 ,  H05K7/20

Abstract: Memory modules comprise memory chips coupled to a surface of one or more substrates. The memory chips contain large numbers of storage cells that consume power during normal operation, generating heat in the memory chips and causing temperatures to increase. As the temperatures increase, leakage currents can increase in the memory chips, and performance of the memory chips can decrease. A memory module includes memory chips disposed on a substrate and an active cooling device disposed on the substrate to increase the rate at which heat is dissipated to reduce or maintain temperatures and thereby save power and improve performance. In some examples, the active cooling device is disposed on a side of a memory chip opposite to the card in the memory module to improve cooling of the memory chips. In some examples, the active cooling device is a thermoelectric device.

公开(公告)号：US20230305922A1

公开(公告)日：2023-09-28

申请号：US17703362

申请日：2022-03-24

Applicant: SMART Modular Technologies, Inc.

Inventor： Robert Tower Frey ,  Kelvin Marino

IPC: G06F1/30 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F1/30 ,  G06F11/0772 ,  G06F11/0793 ,  G06F13/4282

Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system including: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device with data, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.

公开(公告)号：US10510432B1

公开(公告)日：2019-12-17

申请号：US15659420

申请日：2017-07-25

Applicant: SMART Modular Technologies, Inc.

Inventor： Jinying Shen

IPC: G11C29/56 ,  G06F11/22 ,  G06F11/263 ,  G06F12/16 ,  G11C5/04 ,  G06F3/06

Abstract: Approaches, techniques, and mechanisms are disclosed for a test adapter designed to improve testability of non-volatile dual in-line memory modules (NVDIMM) on automatic test equipment (ATE) testers or in-system boards, which have inadequate power supplies. An NVDIMM includes both volatile memories and non-volatile memories. A test adapter is designed to supply increased power to an NVDIMM. A test adapter is implemented using an interposer or a printed circuit board (PCB) that may be inserted into a socket on an ATE tester or on an end-user system-level board. The interposer or PCB includes a power socket for attaching a power cable to supply the external power supply to the NVDIMM. A power on/off sequence is controlled by an ATE tester to simulate or test a system power on/off sequence. An external input power is always on, but both serial and backup power signals are only on during tests of an NVDIMM.

公开(公告)号：US10185609B2

公开(公告)日：2019-01-22

申请号：US15388704

申请日：2016-12-22

Applicant: SMART Modular Technologies, Inc.

Inventor： Shu-Cheng Lin

IPC: G06F11/07 ,  G06F3/06 ,  G11C29/52 ,  G11C16/34 ,  G06F11/10 ,  G11C29/42 ,  G11C29/50 ,  G11C29/04

Abstract: Approaches, techniques, and mechanisms are disclosed for improving data retention using a virtual timer. A memory controller may use a raw bit error rate (RBER) to find an equivalent temperature-accelerated data age of a data item. The data age is computed by using the initial RBER of virtual timing data (VTD) as a virtual write in time of the data item compared to a present time using the current RBER of the VTD. When the data age is determined to exceed a data retention threshold, a data refresh is performed on the data item at the memory block on the memory device. The data age may be stored as virtual timing data on the memory block.