公开(公告)号：US20140034465A1

公开(公告)日：2014-02-06

申请号：US13961279

申请日：2013-08-07

Applicant: OMRON Corporation

Inventor： Takahiro Masuda ,  Naoki Yoshitake ,  Kenichi Hinuma ,  Junya Yamamoto ,  Takashi Fujisawa ,  Takeshi Fujiwara

IPC: H01H1/06

CPC classification number: H01H1/06 ,  B81B2201/014 ,  B81C1/00166 ,  B81C2201/0177 ,  B81C2201/0181 ,  B81C2201/0184 ,  H01H1/0036 ,  H01H2001/0052 ,  Y10T29/49105

Abstract: A switch and a relay include a contact with a smooth contacting surface. A side surface of a fixed contact faces a side surface of a movable contact. The fixed contact has an insulating layer and a base layer stacked on a fixed contact substrate, and a first conductive layer formed thereon through electrolytic plating. The side surface of the first conductive layer that faces the movable contact becomes the fixed contact (contacting surface). The movable contact has an insulating layer and a base layer stacked on the movable contact substrate, and a movable contact formed thereon through electrolytic plating. A side surface of a second conductive layer that faces the fixed contact becomes the movable contact (contacting surface). The fixed contact and the movable contact have surfaces that contact the side surfaces of the mold portion when growing the first and second conductive layers through electrolytic plating.

Abstract translation: 开关和继电器包括具有光滑接触表面的触点。 固定触点的侧表面面对活动触点的侧表面。 固定触点具有层叠在固定接触基板上的绝缘层和基层，以及通过电解电镀形成在其上的第一导电层。 第一导电层的面对可动触点的侧表面成为固定触点（接触面）。 可动触头具有堆叠在可动触点基板上的绝缘层和基极层，以及通过电解电镀形成的可动触点。 面对固定触点的第二导电层的侧表面成为可动触头（接触面）。 固定触点和可动触点具有通过电解电镀生长第一和第二导电层时与模具部分的侧表面接触的表面。

公开(公告)号：US20120286903A1

公开(公告)日：2012-11-15

申请号：US13468052

申请日：2012-05-10

Applicant: Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

Inventor： Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

IPC: H01P7/00 ,  G06F17/50

CPC classification number: B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0271 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0177 ,  G06F17/5045 ,  H03H9/02448 ,  H03H9/2447 ,  H03H2009/2442

Abstract: The invention relates to a micromechanical device comprising a semiconductor element capable of deflecting or resonating and comprising at least two regions having different material properties and drive or sense means functionally coupled to said semiconductor element. According to the invention, at least one of said regions comprises one or more n-type doping agents, and the relative volumes, doping concentrations, doping agents and/or crystal orientations of the regions being configured so that the temperature sensitivities of the generalized stiffness are opposite in sign at least at one temperature for the regions, and the overall temperature drift of the generalized stiffness of the semiconductor element is 50 ppm or less on a temperature range of 100° C. The device can be a resonator. Also a method of designing the device is disclosed.

Abstract translation: 本发明涉及一种微机械装置，其包括能够偏转或谐振并且包括具有不同材料特性的至少两个区域的半导体元件和功能性耦合到所述半导体元件的驱动或感测装置。 根据本发明，所述区域中的至少一个包括一种或多种n型掺杂剂，并且所述区域的相对体积，掺杂浓度，掺杂剂和/或晶体取向被构造成使得广义刚度的温度敏感度 在区域的至少一个温度下符号相反，半导体元件的整体刚度的总体温度漂移在100℃的温度范围内为50ppm以下。该器件可以是谐振器。 还公开了一种设计该设备的方法。

公开(公告)号：USRE41889E1

公开(公告)日：2010-10-26

申请号：US10360367

申请日：2003-02-05

Applicant: Paolo Ferrari ,  Benedetto Vigna ,  Pietro Montanini ,  Marco Ferrera

Inventor： Paolo Ferrari ,  Benedetto Vigna ,  Pietro Montanini ,  Marco Ferrera

IPC: H01L21/00

CPC classification number: H01L21/764 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00246 ,  B81C2201/0109 ,  B81C2201/0177 ,  B81C2203/0735 ,  B81C2203/0778 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  H01L21/76202

Abstract: A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.

Abstract translation: 从外延层开始形成形成地震质量块的移动体，并且由具有高密度的钨的加权区域覆盖。 为了制造质量，在衬底中形成掩埋的导电区域。 然后，同时，在要形成可移动物体的区域中形成牺牲区域，并且在掩埋的导电区域上形成氧化物绝缘区域，以便部分地覆盖它们。 然后使用核区域生长外延层。 沉积和限定钨层，并且使用碳化硅层作为掩模，限定悬浮结构。 最后，去除牺牲区域，形成气隙。

公开(公告)号：US20040048430A1

公开(公告)日：2004-03-11

申请号：US10655839

申请日：2003-09-04

Inventor： Hubert Benzel ,  Hans Artmann ,  Frank Schaeffer

IPC: H01L021/8238

CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81C2201/0115 ,  B81C2201/0177 ,  G01L9/0042

Abstract: A semiconductor component and a method for a semiconductor substrate, in which a first section and a second section are provided, and in which the pore structure of the first section differs from the pore structure of the second section.

Abstract translation: 一种半导体元件和半导体衬底的方法，其中设置有第一部分和第二部分，并且其中第一部分的孔结构与第二部分的孔结构不同。

公开(公告)号：US06376291B1

公开(公告)日：2002-04-23

申请号：US09558959

申请日：2000-04-25

Applicant: Gabriele Barlocchi ,  Flavio Villa ,  Pietro Corona

Inventor： Gabriele Barlocchi ,  Flavio Villa ,  Pietro Corona

IPC: H01L21338

CPC classification number: B81C1/00047 ,  B01L3/5027 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/0177 ,  H01L21/764

Abstract: A process of forming on a monocrystalline-silicon body an etching-aid region of polycrystalline silicon; forming, on the etching-aid region a nucleus region of polycrystalline silicon surrounded by a protective structure having an opening extending as far as the etching-aid region; TMAH-etching the etching-aid region and the monocrystalline body to form a tub-shaped cavity; removing the top layer of the protective structure; and growing an epitaxial layer on the monocrystalline body and the nucleus region. The epitaxial layer, of monocrystalline type on the monocrystalline body and of polycrystalline type on the nucleus region, closes upwardly the etching opening, and the cavity is thus completely embedded in the resulting wafer.

Abstract translation: 在单晶硅体上形成多晶硅的蚀刻助剂区域的工艺; 在所述蚀刻助剂区域上形成由保护结构包围的多晶硅的核区域，所述保护结构具有延伸到所述蚀刻助剂区域的开口; TMAH蚀刻蚀刻助剂区域和单晶体体以形成桶形空腔; 去除保护结构的顶层; 并在单晶体和核区域上生长外延层。 在单晶体上的单晶型的外延层和在核区上的多晶型的外延层向上封闭蚀刻开口，并且因此该空腔完全嵌入所得的晶片中。

公开(公告)号：US06184051B2

公开(公告)日：2001-02-06

申请号：US09479189

申请日：2000-01-07

Applicant: Paolo Ferrari ,  Benedetto Vigna

Inventor： Paolo Ferrari ,  Benedetto Vigna

IPC: H01L2100

CPC classification number: H01L21/764 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00246 ,  B81C2201/0109 ,  B81C2201/0177 ,  B81C2203/0735 ,  B81C2203/0778 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  H01L21/76202

Abstract: A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.

Abstract translation: 从外延层开始形成形成地震质量块的移动体，并且由具有高密度的钨的加权区域覆盖。 为了制造质量，在衬底中形成掩埋的导电区域。 然后，同时，在要形成可移动物体的区域中形成牺牲区域，并且在掩埋的导电区域上形成氧化物绝缘区域，以便部分地覆盖它们。 然后使用核区域生长外延层。 沉积和限定钨层，并且使用碳化硅层作为掩模，限定悬浮结构。 最后，去除牺牲区域，形成气隙。

公开(公告)号：US11952268B2

公开(公告)日：2024-04-09

申请号：US17304094

申请日：2021-06-14

Applicant: Lawrence Semiconductor Research Laboratory, Inc.

Inventor： Chantal Arena ,  Nupur Bhargava ,  Alec Fischer

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00476 ,  B81B3/0072 ,  B81B2203/0118 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0177

Abstract: A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

公开(公告)号：US20180143352A1

公开(公告)日：2018-05-24

申请号：US15325448

申请日：2016-12-28

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Guowei ZHA

IPC: G02B1/113 ,  C03C17/34 ,  C03C17/23 ,  C01B32/186 ,  C01B32/188 ,  B32B3/30 ,  B81C1/00 ,  B82B3/00

CPC classification number: G02B1/113 ,  B32B3/30 ,  B81C1/00555 ,  B81C2201/0177 ,  B82B3/0095 ,  C01B32/186 ,  C01B32/188 ,  C01B2204/20 ,  C03C17/23 ,  C03C17/3441 ,  C03C2217/734 ,  G02B1/118

Abstract: A manufacturing method of micro-nano structure antireflective coating layer and a display apparatus thereof are described. The method includes providing a substrate, forming a silicon oxide layer on the substrate, forming a graphene layer with a hexagonal honeycomb lattice on the silicon oxide layer, and forming a bottom surface of the antireflective coating layer in the nucleation points by serving the graphene layer as a growing base layer, wherein a diffusion length and an atomic mass of diffusion atoms of the antireflective coating layer are decreased with time by a gradient growing manner to form a upper surface of the antireflective coating layer.

公开(公告)号：US20160137485A1

公开(公告)日：2016-05-19

申请号：US14201453

申请日：2014-03-07

Applicant: Robert Bosch GmbH

Inventor： Andrew Graham ,  Gary Yama ,  Gary O'Brien

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  B81B2203/04 ,  B81B2203/053 ,  B81C1/00095 ,  B81C1/00166 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/0177 ,  B81C2203/0136

Abstract: In one embodiment, a method of forming an out-of-plane electrode includes forming an oxide layer above an upper surface of a device layer, etching an etch stop perimeter defining trench extending through the oxide layer, forming a first cap layer portion on an upper surface of the oxide layer and within the etch stop perimeter defining trench, etching a first electrode perimeter defining trench extending through the first cap layer portion and stopping at the oxide layer, depositing a first material portion within the first electrode perimeter defining trench, depositing a second cap layer portion above the deposited first material portion, and vapor releasing a portion of the oxide layer with the etch stop portion providing a lateral etch stop.

Abstract translation: 在一个实施例中，形成平面外电极的方法包括在器件层的上表面上形成氧化物层，蚀刻限定延伸穿过氧化物层的沟槽的蚀刻停止周界，在第一帽层部分上形成 氧化物层的上表面，并且在蚀刻停止周界内限定沟槽，蚀刻延伸穿过第一盖层部分并停止在氧化物层处的第一电极周界，限定沟槽，在第一电极周界限定沟槽内沉积第一材料部分，沉积 在沉积的第一材料部分上方的第二盖层部分，以及用蚀刻停止部分提供横向蚀刻停止物的一部分氧化物层的蒸气。

公开(公告)号：US08558643B2

公开(公告)日：2013-10-15

申请号：US13468052

申请日：2012-05-10

Applicant: Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

Inventor： Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

IPC: H03H9/24 ,  H03H3/013 ,  H01L29/06 ,  H01L21/00

CPC classification number: B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0271 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0177 ,  G06F17/5045 ,  H03H9/02448 ,  H03H9/2447 ,  H03H2009/2442

Abstract: The invention relates to a micromechanical device comprising a semiconductor element capable of deflecting or resonating and comprising at least two regions having different material properties and drive or sense means functionally coupled to said semiconductor element. According to the invention, at least one of said regions comprises one or more n-type doping agents, and the relative volumes, doping concentrations, doping agents and/or crystal orientations of the regions being configured so that the temperature sensitivities of the generalized stiffness are opposite in sign at least at one temperature for the regions, and the overall temperature drift of the generalized stiffness of the semiconductor element is 50 ppm or less on a temperature range of 100° C. The device can be a resonator. Also a method of designing the device is disclosed.

Abstract translation: 本发明涉及一种微机械装置，其包括能够偏转或谐振并且包括具有不同材料特性的至少两个区域的半导体元件和功能性耦合到所述半导体元件的驱动或感测装置。 根据本发明，所述区域中的至少一个包括一种或多种n型掺杂剂，并且所述区域的相对体积，掺杂浓度，掺杂剂和/或晶体取向被构造成使得广义刚度的温度敏感度 在区域的至少一个温度下符号相反，半导体元件的整体刚度的总体温度漂移在100℃的温度范围内为50ppm以下。该器件可以是谐振器。 还公开了一种设计该设备的方法。