公开(公告)号：US07323142B2

公开(公告)日：2008-01-29

申请号：US10038276

申请日：2002-01-02

Applicant: Shaun Pendo ,  Rajiv Shah ,  Edward Chernoff

Inventor： Shaun Pendo ,  Rajiv Shah ,  Edward Chernoff

IPC: G01N27/06 ,  G01N33/66

CPC classification number: H05K3/28 ,  A61B5/0006 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2203/082 ,  H05K2203/085 ,  H05K2203/1147 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K2203/308

Abstract: A substrate with hermetically sealed vias extending from one side of the substrate to another and a method for fabricating same. The vias may be filled with a conductive material such as, for example, a fritless ink. The conductive path formed by the conductive material aids in sealing one side of the substrate from another. One side of the substrate may include a sensing element and another side of the substrate may include sensing electronics.

Abstract translation: 具有从衬底的一侧延伸到另一侧的气密密封通孔的衬底及其制造方法。 通孔可以填充有导电材料，例如无油墨。 由导电材料形成的导电路径有助于将基板的一侧与另一侧密封。 衬底的一侧可以包括感测元件，并且衬底的另一侧可以包括感测电子器件。

公开(公告)号：US20070236896A1

公开(公告)日：2007-10-11

申请号：US11714514

申请日：2007-03-05

Applicant: Masayoshi Takeuchi ,  Shinji Murata

Inventor： Masayoshi Takeuchi ,  Shinji Murata

IPC: H05K7/00 ,  H05K1/18

CPC classification number: H05K3/4061 ,  H05K3/246 ,  H05K2201/0317 ,  H05K2201/0347 ,  H05K2201/09481 ,  H05K2203/0716 ,  H05K2203/072 ,  Y10T29/49124

Abstract: A wiring board in which silver is deposited near a via-conductor includes a ceramic substrate having a via-hole, a via-conductor disposed in the via-hole, and a metal thin-film pattern which is disposed on the ceramic substrate such that the metal thin-film pattern is connected to the via-conductor. The via-conductor contains silver or a material principally containing silver. A silver deposit that is a piece of the via-conductor is disposed on a surface portion of the ceramic substrate that is located near the via-hole. A catalyst layer containing a metal material is disposed over an exposed face of the via-conductor and the surface portion of the ceramic substrate. A metal layer is disposed on the catalyst layer. The metal thin-film pattern is disposed over the metal layer and the ceramic substrate.

Abstract translation: 其中银沉积在通孔导体附近的布线板包括具有通孔的陶瓷基板，设置在通孔中的通路导体和设置在陶瓷基板上的金属薄膜图案，使得 金属薄膜图案连接到通孔导体。 通孔导体包含银或主要含有银的材料。 作为通路导体的一块的银沉积物设置在位于通孔附近的陶瓷基板的表面部分上。 包含金属材料的催化剂层设置在通孔导体和陶瓷基板的表面部分的暴露面上。 金属层设置在催化剂层上。 金属薄膜图案设置在金属层和陶瓷基板上。

公开(公告)号：US07244370B2

公开(公告)日：2007-07-17

申请号：US10910271

申请日：2004-08-04

Applicant: Keiichi Sasaki ,  Masato Kamiichi ,  Yukihiro Hayakawa ,  Ershad Ali Chowdhury

Inventor： Keiichi Sasaki ,  Masato Kamiichi ,  Yukihiro Hayakawa ,  Ershad Ali Chowdhury

IPC: G01D15/00 ,  G11B5/127 ,  H01B13/00

CPC classification number: H05K1/167 ,  B41J2/14072 ,  B41J2/14129 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2/1646 ,  H05K1/09 ,  H05K3/06 ,  H05K3/067 ,  H05K2201/0317 ,  H05K2203/0361

Abstract: In order to provide a circuit substrate with a satisfactory step coverage by the protective layer and the anti-cavitation film in an edge portion of wirings and a liquid discharge head utilizing such circuit substrate, the invention provides a method for producing a circuit substrate provided, on an insulating surface of a substrate, with a plurality of elements each including a resistive layer and a pair of electrodes formed with a predetermined spacing on said resistive layer, including a step of forming an aluminum electrode wiring layer on the resistive layer, a step of isolating the electrode wiring layer by dry etching into each element, and a step of forming the electrode wiring into a tapered cross section with an etching solution containing phosphoric acid, nitric acid and a chelating agent capable of forming a complex with the wiring metal.

Abstract translation: 为了通过利用这种电路基板的布线边缘部分中的保护层和防空穴膜提供令人满意的阶梯覆盖的电路基板，本发明提供一种制造电路基板的方法， 在基板的绝缘表面上，多个元件各自包括电阻层和在所述电阻层上以预定间隔形成的一对电极，包括在电阻层上形成铝电极布线层的步骤，步骤 通过干蚀刻将电极配线层隔离成各元件，以及通过含有与配线金属形成络合物的磷酸，硝酸和螯合剂的蚀刻液将电极配线形成为锥形截面的工序。

公开(公告)号：US20070139150A1

公开(公告)日：2007-06-21

申请号：US11300860

申请日：2005-12-15

Applicant: Eugene Chow ,  Christopher Chua ,  Koenraad Van Schuylenbergh

Inventor： Eugene Chow ,  Christopher Chua ,  Koenraad Van Schuylenbergh

IPC: H01F5/00

CPC classification number: H05K3/4092 ,  H01F17/0006 ,  H01F17/0033 ,  H01F17/02 ,  H01F41/041 ,  H01F2027/2814 ,  H05K3/243 ,  H05K2201/0166 ,  H05K2201/0317 ,  H05K2201/0397 ,  H05K2203/0597 ,  H05K2203/0783

Abstract: A method of reflowing a polymer to form a spring or coil structure is described. A polymer is deposited over stress engineered thin film with an internal stress gradient. The polymer serves as a loading prevent release of the internal stress until a solvent vapor softens and reflows the polymer. As the polymer softens, the internal stress within the thin film is gradually released allowing controlled curling of the thin film out of a substrate plane. In one embodiment, the thin film forms the windings of a coil structure.

Abstract translation: 描述了一种回流聚合物以形成弹簧或线圈结构的方法。 聚合物沉积在具有内应力梯度的应力工程薄膜上。 聚合物用作负载，防止释放内部应力，直到溶剂蒸气软化和回流聚合物。 当聚合物软化时，薄膜内的内部应力逐渐释放，从而允许薄膜从基板平面受到控制的卷曲。 在一个实施例中，薄膜形成线圈结构的绕组。

公开(公告)号：US07154045B2

公开(公告)日：2006-12-26

申请号：US10289178

申请日：2002-11-07

Applicant: Yasunari Ooyabu ,  Takashi Oda ,  Shinichi Oda

Inventor： Yasunari Ooyabu ,  Takashi Oda ,  Shinichi Oda

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/0259 ,  H05K3/28 ,  H05K2201/0317 ,  H05K2201/0326

Abstract: A wired circuit board having a semi-conducting layer which has excellent chemical resistance, such as acid resistance and alkali resistance, provides no possibility of minute particles being mixed into parts mounted on the wired circuit board; and yet has excellent surface resistivity against electrostatic damage. In the wired circuit board having a conductive layer formed on one side of a base insulating layer in the form of a predetermined wired circuit pattern and a cover insulating layer formed on the conductive layer, a base-side semi-conducting layer and a cover-side semi-conducting layer, which include metal oxide, metal nitride or metal carbide, are formed on the other side of the base insulating layer and the cover insulating layer, respectively, by physical vapor deposition (PVD) or preferably by sputtering.

Abstract translation: 具有耐酸性和耐碱性优异的耐化学性的半导体层的布线电路板不会将微小颗粒混入安装在布线电路板上的部件中; 并且具有优异的抗静电损伤的表面电阻率。 在具有形成在预定布线电路图案形式的基底绝缘层的一侧上的导电层和形成在导电层上的覆盖绝缘层的布线电路板中，基底侧半导电层和覆盖层 通过物理气相沉积（PVD）或优选通过溅射分别在基底绝缘层和覆盖绝缘层的另一侧上形成包括金属氧化物，金属氮化物或金属碳化物的侧面半导电层。

公开(公告)号：US20060269730A1

公开(公告)日：2006-11-30

申请号：US11439307

申请日：2006-05-24

Applicant: Jun Ishii ,  Yasuhito Funada ,  Yasunari Ooyabu

Inventor： Jun Ishii ,  Yasuhito Funada ,  Yasunari Ooyabu

IPC: B32B3/00 ,  B32B17/00 ,  B05D5/12

CPC classification number: H05K1/0259 ,  H05K1/056 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0317 ,  H05K2203/0315 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A wired circuit board that can remove static electricity not only from an insulating base layer and an insulating cover layer but also from a terminal portion, to effectively prevent an electronic component mounted from being damaged by static electricity and also prevent stripping of a semi-conductive layer. In a suspension board with circuit including an insulating base layer formed on a metal supporting board, a conductive pattern formed on the insulating base layer, and an insulating cover layer, formed on the insulating cover layer, to cover the conductive pattern and form an opening, semi-conductive layer is formed in succession on an upper surface of the insulating base layer covered with the insulating cover layer, on a lateral side surface and an upper surface of the conductive pattern, and on a lateral side surface of the insulating base layer adjacent to the metal supporting board.

公开(公告)号：US20060094156A1

公开(公告)日：2006-05-04

申请号：US10976878

申请日：2004-11-01

Applicant: Zao-Kuo Lai ,  Lin-Yin Wong

Inventor： Zao-Kuo Lai ,  Lin-Yin Wong

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: H01L23/49822 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K1/095 ,  H05K1/167 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2203/1453 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.

Abstract translation: 提出了一种具有嵌入式电阻器的半导体封装基板及其制造方法。 首先，在其上设置有第一电路层的内部电路板，并且在第一电路层中形成多个电阻电极。 然后，在内部电路板上形成图形化的电阻材料，并电连接到电阻器电极，以精确地限定电阻器的电阻值。 随后，在具有图案化电阻材料的电路板的表面上涂覆至少一个绝缘层。 至少一个图案化的第二电路层形成在绝缘层上，并且通过形成在绝缘层中的多个导电通孔或通过电路板形成的电镀通孔形成在电阻器电极上。

公开(公告)号：US20060024901A1

公开(公告)日：2006-02-02

申请号：US10909877

申请日：2004-08-02

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H01L21/20 ,  H01L21/44

CPC classification number: H01L21/32051 ,  H01C17/065 ,  H01L21/76838 ,  H01L27/013 ,  H05K1/092 ,  H05K1/167 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/0391

Abstract: A method for fabricating a high-frequency and high-power semiconductor module uses two stages respectively adopting a thick-film process to form resistors or elements of high impedance, and a thin film process to form precise circuit wires or elements.

Abstract translation: 高频大功率半导体模块的制造方法分别采用两层分别采用厚膜工艺形成电阻器或高阻抗元件，以及薄膜工艺以形成精确的电路线或元件。

公开(公告)号：US20050205197A1

公开(公告)日：2005-09-22

申请号：US11127373

申请日：2005-05-11

Applicant: Kriss Bennett ,  Roy Coyle

Inventor： Kriss Bennett ,  Roy Coyle

IPC: B32B3/00 ,  B32B18/00 ,  C03B29/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09

CPC classification number: B32B18/00 ,  B32B2315/02 ,  C04B2235/963 ,  C04B2237/343 ,  C04B2237/346 ,  C04B2237/58 ,  C04B2237/582 ,  H05K1/0242 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/0195 ,  H05K2201/0317 ,  H05K2201/0352 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/24942

Abstract: Ceramic substrates (1) for microelectronic modules are formed in multiple layers (7 & 9) fused into a unitary one-piece assembly. The layers contain the same ceramic material but in different purity so that one outer layer (9) is optimal in composition for bonding to a thick film conductor (11) and the other outer layer (7) is optimal in composition for bonding to a thin film conductor (13). In a dual composition substrate embodiment one layer is formed of a 96% alumina composition and the second layer is formed of a 99.6% alumina composition.

Abstract translation: 用于微电子模块的陶瓷基板（1）形成为多层（7＆9），熔合成一体的单件式组件。 这些层包含相同的陶瓷材料，但是具有不同的纯度，使得一个外层（9）在组合物中是最佳的，用于粘合到厚膜导体（11），另一个外层（7）在组合物中是最佳的，用于粘结到薄 薄膜导体（13）。 在双组分基材实施方案中，一层由96％氧化铝组合物形成，第二层由99.6％的氧化铝组成形成。

公开(公告)号：US20050144767A1

公开(公告)日：2005-07-07

申请号：US11068884

申请日：2005-03-02

Applicant: Hiroko Koike ,  Takashi Mochizuki ,  Mitsutoshi Higashi

Inventor： Hiroko Koike ,  Takashi Mochizuki ,  Mitsutoshi Higashi

IPC: H05K1/16 ,  H01G4/33 ,  H01G9/00 ,  H01G9/15 ,  H01L21/20 ,  H01L21/48 ,  H01L21/8242 ,  H01L23/498 ,  H01L51/40 ,  H05K3/30 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01G9/15 ,  H01L21/4857 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/0315 ,  Y10S438/957 ,  Y10T29/417 ,  H01L2924/00

Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a capacitor, and a method of production of the circuit board.

Abstract translation: 一种电容器形成电容器的形成方法，其特征在于，在制造电路基板时形成电路的一部分，其特征在于，在其上形成阀金属底电极层和阀金属氧化物电介质层，然后一体地形成由有机物构成的固体电解质层 半导体和由其上的金属组成的顶部电极层，该整体形成步骤包括将一个金属箔的表面保持在键合楔形件的顶部电极的一个表面，并使金属箔的另一个表面携带 通过压接和加热的有机半导体，以及通过金属箔通过接合楔将电介质层压接的有机半导体粉末压接的步骤，由此夹在金属箔和电介质之间的有机半导体构成的固体电解质层 形成两层紧密结合的电容器，内置于电路板的电容器，电路 其电路板包括电容器，以及生产电路板的方法。