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    PRINTED CIRCUIT BOARD
    31.
    发明申请
    PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板

    公开(公告)号：US20140060896A1

    公开(公告)日：2014-03-06

    申请号：US13827429

    申请日：2013-03-14

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Gil Yong SHIN ,  Seung Lak Kim ,  Kyoung Ro Yoon

    IPC: H05K1/02

    CPC classification number: H05K1/0201 ,  H05K1/09 ,  H05K3/0035 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/0341

    Abstract: Disclosed herein is a printed circuit board, including: an insulating layer; a circuit layer formed on one surface of the insulating layer; and a via electrode penetrating through the insulating layer and being connected with the circuit layer, wherein the circuit layer is formed in a structure where different kinds of metal layers having different thermal conductivities are laminated.

    Abstract translation: 这里公开了一种印刷电路板，包括：绝缘层; 形成在所述绝缘层的一个表面上的电路层; 以及穿过所述绝缘层并与所述电路层连接的通孔电极，其中所述电路层形成为层叠不同导热系数的不同种类的金属层的结构。

    PROCESS FOR FABRICATING CIRCUIT BOARD
    35.
    发明申请
    PROCESS FOR FABRICATING CIRCUIT BOARD 审中-公开
    制造电路板的工艺

    公开(公告)号：US20120124830A1

    公开(公告)日：2012-05-24

    申请号：US13362958

    申请日：2012-01-31

    Applicant: David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

    Inventor： David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

    IPC: H05K3/10

    CPC classification number: H05K3/4007 ,  H05K3/06 ,  H05K3/062 ,  H05K3/107 ,  H05K3/3452 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

    Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.

    Abstract translation: 提供一种制造电路板的工艺。 在该过程中，首先，提供包括绝缘层和至少与绝缘层接触的焊盘的电路基板。 接下来，在电路基板上形成阻挡材料层。 阻挡材料层完全覆盖绝缘层和垫。 然后，在阻挡材料层上形成至少一个导电凸块。 导电凸块与焊盘相对，并且阻挡材料层的材料与导电凸块的材料不同。 接下来，通过使用导电凸块作为掩模来去除阻挡材料层的一部分，以暴露绝缘层的表面并形成连接在导电凸块和焊盘之间的阻挡层。

    Packaging substrate with conductive structure
    36.
    发明授权
    Packaging substrate with conductive structure 有权
    具有导电结构的封装基板

    公开(公告)号：US08101866B2

    公开(公告)日：2012-01-24

    申请号：US12175348

    申请日：2008-07-17

    Applicant: Shih-Ping Hsu

    Inventor： Shih-Ping Hsu

    IPC: H01R9/00

    CPC classification number: H05K3/3473 ,  H01L23/498 ,  H01L23/49816 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13565 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/099 ,  H05K2203/054 ,  H01L2224/05552

    Abstract: A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

    Abstract translation: 提供一种具有导电结构的封装基板，包括：具有在其表面上至少有一个导电焊盘的基板主体，设置在导电焊盘上的应力缓冲金属层，设置在基板主体上的阻焊层，并具有至少一个开口 用于相应地暴露应力缓冲金属层的顶表面的一部分，设置在应力缓冲金属层的表面的中心部分上的金属柱和覆盖金属柱的表面的焊料凸块。 因此，通过使用应力缓冲金属层来释放热应力，并且使用金属柱和焊料凸块来增加导电结构的高度，提供了高度可靠的导电结构。

    METHOD OF MANUFACTURING MULTILAYER PRINTED WIRING BOARD
    37.
    发明申请
    METHOD OF MANUFACTURING MULTILAYER PRINTED WIRING BOARD 有权
    制造多层印刷线路板的方法

    公开(公告)号：US20110272286A1

    公开(公告)日：2011-11-10

    申请号：US13187060

    申请日：2011-07-20

    Applicant: Toru NAKAI ,  Sho Akai

    Inventor： Toru NAKAI ,  Sho Akai

    IPC: C25D5/02 ,  C25D7/00

    CPC classification number: H05K3/4644 ,  H05K3/108 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/073 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165

    Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

    Abstract translation: 一种制造多层印刷线路板的方法包括在第一层间树脂绝缘层上形成第一层间树脂绝缘层，第一导体电路，第二层间树脂绝缘层，第二层间树脂绝缘层中的开口部分，露出面 第一导体电路的第二层间树脂绝缘层上的无电镀膜和暴露面，以及化学镀膜上的电镀抗蚀剂。 该方法还包括用具有比无电镀膜低的离子倾向的薄膜导体层和暴露面的金属代替化学镀膜，在化学镀膜的一部分上形成包括金属的电镀膜 和薄膜导体层，剥离电镀抗蚀剂，以及除去通过剥离暴露的化学镀膜。

    Circuit board and method for fabricating the same
    38.
    发明申请
    Circuit board and method for fabricating the same 审中-公开
    电路板及其制造方法

    公开(公告)号：US20090071704A1

    公开(公告)日：2009-03-19

    申请号：US12284324

    申请日：2008-09-19

    Applicant: Shih-Ping Hsu

    Inventor： Shih-Ping Hsu

    IPC: H05K1/11 ,  H05K3/10

    CPC classification number: H05K3/465 ,  H05K1/09 ,  H05K3/184 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4661 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/0733 ,  Y10T29/49155

    Abstract: A circuit board and a method for fabricating the same are disclosed. The circuit board includes: a carrier board having a circuit layer formed on at least one surface thereof; a first dielectric layer formed on the carrier board and having first openings for exposing a part of the circuit layer; conductive vias formed in the first openings; a second dielectric layer formed on the first dielectric layer and having second and third openings formed therein, wherein the second openings correspond to the first openings for exposing the conductive vias; and a multi-layered metal electroless plating circuit layer formed in the second and third openings for electrically connecting the circuit layer of the carrier board via the conductive vias, thereby allowing the multi-layered metal electroless plating circuit layer to be embedded into the first and second dielectric layers to enhance the bonding strength therebetween and increase the reliability of the circuit board and facilitate formation of fine circuits.

    Abstract translation: 公开了一种电路板及其制造方法。 电路板包括：承载板，其具有形成在其至少一个表面上的电路层; 第一电介质层，形成在所述载体板上并具有用于暴露所述电路层的一部分的第一开口; 在第一开口中形成的导电通孔; 第二电介质层，形成在所述第一电介质层上并且具有形成在其中的第二和第三开口，其中所述第二开口对应于用于暴露所述导电通孔的所述第一开口; 以及形成在所述第二和第三开口中的多层金属化学镀电路层，用于经由所述导电通孔电连接所述载体板的电路层，从而允许所述多层金属化学镀电路层嵌入所述第一和第 第二电介质层，以增强它们之间的结合强度，并提高电路板的可靠性并促进精细电路的形成。

    Production method of wiring substrate having ultra-fine pattern, and wiring substrate
    39.
    发明申请
    Production method of wiring substrate having ultra-fine pattern, and wiring substrate 审中-公开
    具有超细图案的布线基板的制造方法以及布线基板

    公开(公告)号：US20050269206A1

    公开(公告)日：2005-12-08

    申请号：US11144732

    申请日：2005-06-06

    Applicant: Shuichi Tanaka ,  Kazutaka Kobayashi

    Inventor： Shuichi Tanaka ,  Kazutaka Kobayashi

    IPC: C25D5/02 ,  H05K3/10

    CPC classification number: H05K3/108 ,  H05K2201/0341 ,  H05K2203/0384 ,  H05K2203/073

    Abstract: To produce a wiring substrate by employing a semi-additive method, the invention provides a production method of a wiring substrate, and a wiring substrate, that suppress the formation of undercut of an electrolytic copper plating layer during base etching and capable of ultra-fine wiring of a line/space size of 25/25 μm or below and further 10/10 μm or below. When producing a wiring substrate, the method of the invention includes the steps of applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer; applying a resist pattern exposing a portion for forming a wiring pattern on the surface of the electroless copper plating layer; plating metals different from copper or alloys containing at least one kind of the metals to the exposed portion to form an etching barrier plating layer; plating an etching barrier metal to form an etching barrier metal plating layer; applying electrolytic copper plating to the surface of the etching barrier metal plating layer to form wiring having a conductor layer including an electroless copper plating layer, the etching barrier metal plating layer and the electrolytic copper plating layer and the electrolytic copper plating layer; removing the resist pattern; and etching and removing the electroless copper plating layer exposed on the surface to form a wiring pattern.

    Abstract translation: 为了通过使用半添加法制造布线基板，本发明提供了一种布线基板和布线基板的制造方法，其抑制在基底蚀刻期间电解铜镀层的底切形成，并能够超细 线/间距25/25 mum以下，进一步10/10 mum以下。 在制造布线基板时，本发明的方法包括以下步骤：将无电镀铜施加到由具有电绝缘性的树脂制成的基板的表面上，形成化学镀铜层; 在所述化学镀铜层的表面上施加曝光用于形成布线图案的部分的抗蚀剂图案; 将不同于铜或含有至少一种金属的合金的金属镀覆到暴露部分以形成蚀刻阻挡镀层; 电镀蚀刻阻挡金属以形成蚀刻阻挡金属镀层; 对所述蚀刻阻挡金属镀层的表面进行电解镀铜，形成具有包含无电镀铜层的导电体层，所述蚀刻阻挡金属镀层，所述电解镀铜层和所述电解镀铜层的配线; 去除抗蚀剂图案; 并蚀刻并除去暴露在表面上的化学镀铜层以形成布线图案。

    Buried resist technique for the fabrication of printed wiring
    40.
    发明授权
    Buried resist technique for the fabrication of printed wiring 失效
    用于制造印刷线路的掩埋抗蚀剂技术

    公开(公告)号：US4312897A

    公开(公告)日：1982-01-26

    申请号：US157595

    申请日：1980-06-09

    Applicant: William G. Reimann

    Inventor： William G. Reimann

    IPC: H05K1/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H05K3/42 ,  H05K3/18

    CPC classification number: H05K3/243 ,  H05K1/0265 ,  H05K3/062 ,  H05K3/427 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2203/0384 ,  H05K2203/0574 ,  H05K3/108 ,  H05K3/3473

    Abstract: Narrow conductors and narrow spaces therebetween, typically two or three mils wide, are fabricated on outer layers of a printed wiring board with built-up areas such as plated-through holes or conductors of widths greater than two or three mils. Gold is deposited over a copper clad substrate in a pattern defining the desired circuitry. Thereafter, solder is placed at the built-up areas and, using both the solder and the gold as resist or masks, the exposed copper is removed by etching. An organic resist material is used in lieu of solder when the built-up area comprises wide conductors or leads, e.g., power busses.

    Abstract translation: 典型地为2或3密耳宽的窄导体和狭窄的空间被制造在印刷线路板的外层上，其具有诸如电镀通孔或宽度大于2或3密耳的导体的组合区域。 金以限定所需电路的图案沉积在铜包覆基板上。 此后，将焊料放置在积聚区域，并且使用焊料和金作为抗蚀剂或掩模，通过蚀刻去除暴露的铜。 当组合区域包括宽导体或引线（例如功率总线）时，使用有机抗蚀剂材料代替焊料。

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