公开(公告)号：US08322032B2

公开(公告)日：2012-12-04

申请号：US12720238

申请日：2010-03-09

Applicant: Chih-Cheng Lee

Inventor： Chih-Cheng Lee

IPC: H05K3/46 ,  H05K3/42 ,  H05K3/02

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/0023 ,  H05K3/04 ,  H05K3/045 ,  H05K3/06 ,  H05K3/10 ,  H05K3/108 ,  H05K3/4038 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/0352 ,  H05K2203/025 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.

Abstract translation: 提供了一种用于制造衬底结构的方法。 该方法包括以下步骤。 提供基板。 衬底具有图案化的第一金属层，图案第二金属层和通孔。 之后，分别在基板的第一表面和第二表面上形成第一电介质层和第二电介质层。 第二表面与第一表面相对。 然后，对第一电介质层和第二电介质层进行图案化。 之后，在图案化的第一介电层的表面形成第一迹线层。 第一迹线层被嵌入到图案化的第一介电层中并且与第一介电层共面。 然后，在第二电介质层的表面上形成第二迹线层。

公开(公告)号：US20120291272A1

公开(公告)日：2012-11-22

申请号：US13472937

申请日：2012-05-16

Applicant: Kyung Ho LEE ,  Se Min Oh ,  Chang Hwan Choi ,  Choon Keun Lee ,  Jeong Yeol Moon ,  Jong Rip Kim

Inventor： Kyung Ho LEE ,  Se Min Oh ,  Chang Hwan Choi ,  Choon Keun Lee ,  Jeong Yeol Moon ,  Jong Rip Kim

IPC: H05K3/00

CPC classification number: H05K1/028 ,  H05K1/0218 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/0715 ,  H05K2201/09736 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126

Abstract: An FPCB and a method of manufacturing the same, in which an electrical signal-conductive portion of the FPCB is subjected to little stress so as not to be broken by fatigue in spite of repeated bending of the FPCB, thereby increasing the lifetime of the FPCB.

公开(公告)号：US08314438B2

公开(公告)日：2012-11-20

申请号：US12911729

申请日：2010-10-26

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L33/00

CPC classification number: H05K1/021 ,  H01L21/486 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01087 ,  H01L2924/15153 ,  H05K3/4084 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/10106 ,  H05K2203/049 ,  H05K2203/063 ,  H01L2924/00014

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump, a base and a flange. The conductive trace includes a pad and a terminal. The semiconductor device extends into a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和粘合剂。 散热器包括凸块，底座和凸缘。 导电迹线包括焊盘和端子。 半导体器件延伸到凸块中的空腔中，电连接到导电迹线并且热连接到凸块。 凸起从基部延伸到粘合剂中的开口中，基部从与腔相对的凸起垂直延伸，并且凸缘从腔入口处的凸起横向延伸。 导电迹线位于腔体外部，并在焊盘和端子之间提供信号路由。

公开(公告)号：US08304915B2

公开(公告)日：2012-11-06

申请号：US13055372

申请日：2009-07-23

Applicant: Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

Inventor： Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/10674 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00

Abstract: A semiconductor device includes a plural number of interconnects and a plural number of vias are stacked. A semiconductor element is enclosed in an insulation layer. At least one of the vias provided in insulation layers and/or at least one of interconnects provided in the interconnect layers are of cross-sectional shapes different from those of the vias formed in another one of the insulation layers and/or interconnects provided in another one of the interconnect layers.

Abstract translation: 半导体器件包括多个互连件，并且堆叠多个通孔。 半导体元件封装在绝缘层中。 提供在绝缘层中的至少一个通孔和/或设置在互连层中的至少一个互连件的横截面形状与在另一个绝缘层中提供的另一个绝缘层和/或互连中形成的通孔的截面形状不同 互连层之一。

公开(公告)号：US20120011716A1

公开(公告)日：2012-01-19

申请号：US13137695

申请日：2011-09-02

Applicant: Han Kim ,  Mi Sun Hwang ,  Suk Won Lee ,  Chang Gun Oh

Inventor： Han Kim ,  Mi Sun Hwang ,  Suk Won Lee ,  Chang Gun Oh

IPC: H05K3/42

CPC classification number: H05K3/462 ,  H05K1/0265 ,  H05K1/0366 ,  H05K3/025 ,  H05K3/108 ,  H05K3/4623 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09736 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method of manufacturing a printed circuit board including: preparing a first double-sided substrate including a first insulating layer, a first lower copper layer, a second circuit layer including a first lower land, and a first via; preparing a second double-sided substrate including a second insulating layer, a third lower copper layer, a fourth circuit layer including a second lower land, and a second via; disposing a third insulating layer between the second circuit layer and the fourth circuit layer such that the first lower land and the second lower land are electrically connected to each other though a conductive bump; and forming a first circuit layer including a first circuit pattern connected to the first via on the first lower copper layer and forming a third circuit layer including a third circuit pattern connected to the second via on the third lower copper layer.

Abstract translation: 一种制造印刷电路板的方法，包括：制备包括第一绝缘层，第一下铜层，包括第一下焊盘的第二电路层和第一通孔的第一双面基板; 制备包括第二绝缘层，第三下铜层，包括第二下焊盘的第四电路层和第二通孔的第二双面基板; 在所述第二电路层和所述第四电路层之间设置第三绝缘层，使得所述第一下焊盘和所述第二下焊盘通过导电凸块彼此电连接; 以及形成第一电路层，所述第一电路层包括在所述第一下铜层上连接到所述第一通孔的第一电路图案，并形成第三电路层，所述第三电路层包括在所述第三下铜层上连接到所述第二通孔的第三电路图案。

公开(公告)号：US08085546B2

公开(公告)日：2011-12-27

申请号：US12901104

申请日：2010-10-08

Applicant: Ayao Niki

Inventor： Ayao Niki

IPC: H05K7/00

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49162

Abstract: A coreless multilayer printed wiring board including a coreless layer having an opening, a conductive film formed on an upper surface of the coreless layer and closing one end of the opening of the coreless layer, a via-hole formed in the opening of the coreless layer, a first resin layer formed on the coreless layer and the conductive film and having an opening reaching to the conductive film, a via-hole formed in the opening of the first resin layer, a second resin layer formed on the upper surface of the first resin layer and having an opening, a via-hole formed in the opening of the second resin layer. The via-holes formed in the first and second resin layers are open in the direction opposite to the direction in which the via-hole formed in the coreless layer is open.

Abstract translation: 一种无芯多层印刷线路板，包括具有开口的无芯层，形成在无芯层的上表面上并封闭无芯层的开口的一端的导电膜，形成在无芯层的开口中的通孔 形成在无芯层和导电膜上并具有到达导电膜的开口的第一树脂层，形成在第一树脂层的开口中的通孔，形成在第一树脂层的上表面上的第二树脂层 树脂层并具有开口，形成在第二树脂层的开口中的通孔。 形成在第一和第二树脂层中的通孔在与形成在无芯层中的通孔开放的方向相反的方向上是开放的。

公开(公告)号：US20110303451A1

公开(公告)日：2011-12-15

申请号：US13216767

申请日：2011-08-24

Applicant: Yasushi INAGAKI ,  Katsuyuki Sano

Inventor： Yasushi INAGAKI ,  Katsuyuki Sano

IPC: H05K1/16 ,  H05K1/11

CPC classification number: H05K1/0237 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0224 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09736 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer printed wiring board including a core substrate, a first conductor layer on a first surface of the substrate, a second conductor layer on a second surface of the substrate, a third conductor layer inside the substrate between the first and second conductor layers, a conductive post connecting the third conductor layer with the first and second conductor layers, a first conductor circuit on the first surface of the substrate, a second conductor circuit on the second surface of the substrate, and a through hole formed through the substrate and connecting the first and second conductor circuits. The through hole is not connected to the third conductor layer, the third conductor layer has thickness larger than thicknesses of the first and second conductor layers, each of the first, second and third conductor layers forms one of power supply and ground layers, and the through hole forms a signal line.

Abstract translation: 一种多层印刷布线板，包括芯基板，在基板的第一表面上的第一导体层，在基板的第二表面上的第二导体层，在第一和第二导体层之间的基板内的第三导体层， 将第三导体层与第一和第二导体层连接的导电柱，在基板的第一表面上的第一导体电路，在基板的第二表面上的第二导体电路，以及穿过基板形成的通孔， 第一和第二导体电路。 通孔不连接到第三导体层，第三导体层的厚度大于第一和第二导体层的厚度，第一，第二和第三导体层中的每一个形成电源和接地层中的一个，并且 通孔形成信号线。

公开(公告)号：US20110253306A1

公开(公告)日：2011-10-20

申请号：US13169736

申请日：2011-06-27

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K3/00 ,  B32B38/04

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method of manufacturing a printed circuit board includes the following steps (A) to (D). (A) Laminating a resin insulating layer on each of two sides of a core member to form a core substrate, (B) forming penetrating openings in the core substrate by applying laser beams, (C) forming a rough surface on the core substrate, and (D) providing a metal film for each penetrating opening to form through holes.

Abstract translation: 制造印刷电路板的方法包括以下步骤（A）至（D）。 （A）在芯部件的两侧各自层叠树脂绝缘层，形成芯基板，（B）通过施加激光而在芯基板上形成贯通孔，（C）在芯基板上形成粗糙面， 和（D）为每个穿透孔提供金属膜以形成通孔。

公开(公告)号：US08040201B2

公开(公告)日：2011-10-18

申请号：US12354488

申请日：2009-01-15

Applicant: Kwang-Soo Park ,  Byoung-Ha Oh ,  Yong-Ho Ko

Inventor： Kwang-Soo Park ,  Byoung-Ha Oh ,  Yong-Ho Ko

IPC: H04B3/30 ,  H01P3/08

CPC classification number: H05K1/0216 ,  H05K1/0234 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/167 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09318 ,  H05K2201/09327

Abstract: A substrate includes a power plane and a ground plane that are placed apart from and are substantially parallel to each other, and at least one signal line that is placed between the power plane and the ground plane. The ground plane includes a first conductive layer having a first conductivity. The power plane includes a second conductive layer having the first conductivity, and the power plane or the ground plane includes a third conductive layer having a second conductivity lower than the first conductivity. The third conductive layer faces the at least one signal line across a dielectric substance.

Abstract translation: 基板包括放置在彼此之间并且基本上彼此平行的电源平面和接地平面以及放置在电源平面和接地平面之间的至少一条信号线。 接地平面包括具有第一导电性的第一导电层。 功率平面包括具有第一导电性的第二导电层，并且功率平面或接地平面包括具有比第一导电率低的第二导电性的第三导电层。 第三导电层面对穿过电介质物质的至少一条信号线。

公开(公告)号：US08027169B2

公开(公告)日：2011-09-27

申请号：US11555881

申请日：2006-11-02

Applicant: Ayao Niki

Inventor： Ayao Niki

IPC: H05K7/00

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49162

Abstract: A multilayer printed wiring board includes one or more resin layers having via-holes and a core layer having via-holes. The via-holes formed in the one or more resin layers are open in the direction opposite to the direction in which the via-holes formed in the core layer are open. A method for manufacturing a multilayer printed wiring board includes a step of preparing a single- or double-sided copper-clad laminate; a step of forming lands by processing the copper-clad laminate; a step of forming a resin layer on the upper surface of the copper-clad laminate, forming openings for via-holes in the resin layer, and then forming the via-holes; and a step of forming openings for via-holes in the lower surface of the copper-clad laminate and then forming the via-holes.

Abstract translation: 多层印刷线路板包括一个或多个具有通孔的树脂层和具有通孔的芯层。 在一个或多个树脂层中形成的通孔在与芯层中形成的通路孔打开的方向相反的方向上开口。 一种制造多层印刷线路板的方法包括制备单面或双面覆铜层压板的步骤; 通过加工覆铜层压板来形成焊盘的步骤; 在覆铜层压板的上表面上形成树脂层的步骤，在树脂层中形成通孔的开口，然后形成通孔; 以及在覆铜层压板的下表面中形成用于通孔的开口，然后形成通孔的步骤。