公开(公告)号：US07350298B2

公开(公告)日：2008-04-01

申请号：US11467629

申请日：2006-08-28

Applicant: Shih-Ping Hsu ,  Sao-Hsia Tang ,  Ying-Tung Wang ,  Wen Hung Hu ,  Chao Wen Shih

Inventor： Shih-Ping Hsu ,  Sao-Hsia Tang ,  Ying-Tung Wang ,  Wen Hung Hu ,  Chao Wen Shih

IPC: H01K3/10 ,  H05K3/02 ,  H05K3/34

CPC classification number: H05K3/3484 ,  H05K1/112 ,  H05K3/1216 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0391 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/054 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating a circuit board having a conductive structure is disclosed. The method includes: forming first and second insulating protective layers respectively on first and second surfaces of a circuit board; forming a conductive layer on the first insulating protective layer and the openings; forming first and second resist layers on the conductive layer and the second insulating protective layer respectively; forming first electrically connecting structures by electroplating on the exposed conductive layer over a plurality of first and second electrically connecting pads in openings of the first resist layer; removing the first and the second resist layers and the conductive layer covered by the first resist layer; and forming second electrically connecting structures by stencil printing on the conductive layer over the second electrically connecting pads on the first surface and on a plurality of third electrically connecting pads of the second surface of the circuit board.

Abstract translation: 公开了一种制造具有导电结构的电路板的方法。 该方法包括：分别在电路板的第一和第二表面上形成第一和第二绝缘保护层; 在所述第一绝缘保护层和所述开口上形成导电层; 分别在导电层和第二绝缘保护层上形成第一和第二抗蚀剂层; 通过在所述第一抗蚀剂层的开口中的多个第一和第二电连接焊盘上的暴露的导电层上电镀来形成第一电连接结构; 去除由第一抗蚀剂层覆盖的第一和第二抗蚀剂层和导电层; 以及通过在第一表面上的第二电连接焊盘和电路板的第二表面的多个第三电连接焊盘上的导电层上的模版印刷形成第二电连接结构。

公开(公告)号：US07332801B2

公开(公告)日：2008-02-19

申请号：US10955233

申请日：2004-09-30

Applicant: Ai Ling Low ,  Dejen Eshete

Inventor： Ai Ling Low ,  Dejen Eshete

IPC: H01L29/40

CPC classification number: H05K3/243 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2203/0353 ,  H05K2203/0574 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device includes a first die that includes wires for bonding, a second die that includes an array of balls for bonding, and a substrate. The substrate includes bond sites for wires from the first die, and bond sites for the array of balls from the second die. The wires of first die are coupled to the bond sites for wires of the substrate. The balls of the second die are coupled to the bond sites for the array of balls of the substrate.

Abstract translation: 电子设备包括：第一管芯，其包括用于接合的导线，第二管芯，其包括用于接合的球的阵列;以及基板。 衬底包括用于来自第一裸片的线的接合位置，以及用于来自第二管芯的球阵列的接合位置。 第一管芯的引线与基片的引线的接合位置耦合。 第二管芯的球体连接到衬底阵列的接合位置。

公开(公告)号：US07215555B2

公开(公告)日：2007-05-08

申请号：US10796983

申请日：2004-03-11

Applicant: Kouichi Takagi

Inventor： Kouichi Takagi

IPC: H01R9/00

CPC classification number: H05K3/202 ,  H05K1/029 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2201/10166 ,  H05K2203/175

Abstract: An integrated bus bar structure plate in which a plurality of bus bars are arranged on substantially the one plain face to form an electric power circuit, wherein after the bus bar structure plate having a whole shape in which a plurality of types of electric power circuits are formed by selecting any of the connection parts of the bus bars is separated is adhered to the control circuit board whereby, for example, a desired electric power circuit is formed among the connection parts of bus bars.

Abstract translation: 一种集成汇流条结构板，其中多个汇流条布置在基本上一个平面上以形成电力电路，其中在具有整体形状的汇流条结构板之后，多个类型的电力电路是 通过选择母线的任何一个连接部分形成的分离的部分粘附到控制电路板，由此例如在汇流条的连接部分之间形成期望的电力电路。

公开(公告)号：US07179520B2

公开(公告)日：2007-02-20

申请号：US11019639

申请日：2004-12-23

Applicant: Takayuki Saeki

Inventor： Takayuki Saeki

IPC: B32B9/00 ,  H01K1/03

CPC classification number: H05K1/028 ,  G02F2001/133302 ,  H05K1/0289 ,  H05K2201/0391 ,  H05K2201/09727 ,  H05K2201/09736 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A circuit substrate is described where the circuit substrate has a first wiring group extending in a first direction and a second wiring group extending in a second direction substantially orthogonal to the first direction. The first wiring group of the circuit substrate is stronger than the second wiring group, and the second wiring group bends more easily than the first wiring group, which results in directional flexibility of said circuit substrate.

Abstract translation: 描述电路基板，其中电路基板具有沿第一方向延伸的第一布线组和沿与第一方向大致正交的第二方向延伸的第二布线组。 电路基板的第一布线组比第二布线组强，第二布线组比第一布线组更容易弯曲，这导致所述电路基板的定向灵活性。

公开(公告)号：US20070001295A1

公开(公告)日：2007-01-04

申请号：US11454905

申请日：2006-06-19

Applicant: Jung-Chan Cho ,  Byung-Man Kim ,  Yong-Hyun Kim

Inventor： Jung-Chan Cho ,  Byung-Man Kim ,  Yong-Hyun Kim

IPC: H01L23/34

CPC classification number: H05K3/244 ,  H01L2924/0002 ,  H05K3/243 ,  H05K3/28 ,  H05K3/282 ,  H05K3/427 ,  H05K2201/0391 ,  H05K2203/0574 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same may be provided. The semiconductor device may include an insulation material as a base frame of a PCB, including an opening penetrating the insulation material with sidewalls plated with a gold (Au) layer. The semiconductor device may further include a printed circuit board for use in a module, having a pad whose surface may be coated with an organic solderability preservative (OSP) and an opening whose sidewalls may be plated with a nickel (Ni) layer and a gold (Au) layer, and a semiconductor device mounted on the PCB via the pad. During a temperature cycling reliability test on the semiconductor device, no defects, for example, cracks may form inside the opening.

Abstract translation: 可以提供半导体器件及其制造方法。 半导体器件可以包括作为PCB的基座的绝缘材料，其包括穿透绝缘材料的开口，其侧壁镀有金（Au）层。 半导体器件还可以包括用于模块中的印刷电路板，其具有可以用有机可焊性防腐剂（OSP）涂覆其表面的焊盘，以及其侧壁可镀镍（Ni）层和金 （Au）层，以及通过焊盘安装在PCB上的半导体器件。 在半导体器件的温度循环可靠性测试中，在开口内部不会形成例如裂纹的缺陷。

公开(公告)号：US20060102384A1

公开(公告)日：2006-05-18

申请号：US11250531

申请日：2005-10-17

Applicant: Yasuhiro Watanabe ,  Michimasa Takahashi ,  Masakazu Aoyama ,  Takenobu Nakamura ,  Hiroyuki Yanagisawa

Inventor： Yasuhiro Watanabe ,  Michimasa Takahashi ,  Masakazu Aoyama ,  Takenobu Nakamura ,  Hiroyuki Yanagisawa

IPC: H05K1/09 ,  H05K1/03

CPC classification number: H05K1/113 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/114 ,  H05K3/243 ,  H05K3/28 ,  H05K3/282 ,  H05K3/4614 ,  H05K2201/0391 ,  H05K2201/10674 ,  H05K2203/0574 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49204 ,  H01L2224/0401

Abstract: This invention provides a multilayer printed wiring board in which electric connectivity and functionality are obtained by improving reliability and particularly, reliability to the drop test can be improved. No corrosion resistant layer is formed on a solder pad 60B on which a component is to be mounted so as to obtain flexibility. Thus, if an impact is received from outside when a related product is dropped, the impact can be buffered so as to protect any mounted component from being removed. On the other hand, land 60A in which the corrosion resistant layer is formed is unlikely to occur contact failure even if a carbon pillar constituting an operation key makes repeated contacts.

Abstract translation: 本发明提供了一种通过提高可靠性而获得电连接性和功能性的多层印刷线路板，特别是可提高落下试验的可靠性。 在要安装部件的焊料垫60B上没有形成耐腐蚀层，以获得柔性。 因此，如果在相关产品掉线时从外部接收到冲击，则可以缓冲影响，以保护所安装的组件不被移除。 另一方面，即使构成操作键的碳柱重复接触，也可能不形成耐腐蚀层的焊盘60A接触不良。

公开(公告)号：US20060090335A1

公开(公告)日：2006-05-04

申请号：US11060497

申请日：2005-02-18

Applicant: Shih-Ping Hsu ,  Sao-Hsia Tang ,  Chao-Wen Shih

Inventor： Shih-Ping Hsu ,  Sao-Hsia Tang ,  Chao-Wen Shih

IPC: H01R43/00

CPC classification number: H05K3/243 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11902 ,  H01L2924/00014 ,  H05K3/28 ,  H05K3/3473 ,  H05K2201/0391 ,  H05K2201/09436 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/0574 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for fabricating connection terminals of a circuit board is proposed. The method involves providing a circuit board with connection pads thereon, forming an insulating layer with first openings over the circuit board to expose the connection pads, forming a conductive layer over the insulating layer, forming a first resist layer with second openings over the conductive layer to partially expose the conductive layer, electroplating a first metal connection layer on the exposed conductive layer, followed by forming a second resist layer with third openings over the first conductive layer to partially expose the first metal connection layer, and electroplating a second metal connection layer on the exposed first connection layer, and removing portions of the first and second resist layers and conductive layer covered by the first and second resist layers to form metal connection material of different heights and sizes on the connection pads.

Abstract translation: 提出了一种用于制造电路板的连接端子的方法。 该方法包括为电路板提供其上的连接焊盘，在电路板上形成具有第一开口的绝缘层，以暴露连接焊盘，在绝缘层上形成导电层，形成第一抗蚀剂层，第二开口穿过导电层 以部分地暴露所述导电层，在所述暴露的导电层上电镀第一金属连接层，随后在所述第一导电层上形成具有第三开口的第二抗蚀剂层以部分地暴露所述第一金属连接层，以及电镀第二金属连接层 在所述暴露的第一连接层上，以及去除所述第一和第二抗蚀剂层的部分和由所述第一和第二抗蚀剂层覆盖的导电层，以在所述连接焊盘上形成不同高度和尺寸的金属连接材料。

公开(公告)号：US20060065963A1

公开(公告)日：2006-03-30

申请号：US10955233

申请日：2004-09-30

Applicant: Ai Low ,  Dejen Eshete

Inventor： Ai Low ,  Dejen Eshete

IPC: H01L21/48 ,  H01L23/52

CPC classification number: H05K3/243 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2203/0353 ,  H05K2203/0574 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device includes a first die that includes wires for bonding, a second die that includes an array of balls for bonding, and a substrate. The substrate includes bond sites for wires from the first die, and bond sites for the array of balls from the second die. The wires of first die are coupled to the bond sites for wires of the substrate. The balls of the second die are coupled to the bond sites for the array of balls of the substrate.

Abstract translation: 电子设备包括：第一管芯，其包括用于接合的导线，第二管芯，其包括用于接合的球的阵列;以及基板。 衬底包括用于来自第一裸片的线的接合位置，以及用于来自第二管芯的球阵列的接合位置。 第一管芯的引线与基片的引线的接合位置耦合。 第二管芯的球体连接到衬底阵列的接合位置。

公开(公告)号：US20060024901A1

公开(公告)日：2006-02-02

申请号：US10909877

申请日：2004-08-02

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H01L21/20 ,  H01L21/44

CPC classification number: H01L21/32051 ,  H01C17/065 ,  H01L21/76838 ,  H01L27/013 ,  H05K1/092 ,  H05K1/167 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/0391

Abstract: A method for fabricating a high-frequency and high-power semiconductor module uses two stages respectively adopting a thick-film process to form resistors or elements of high impedance, and a thin film process to form precise circuit wires or elements.

Abstract translation: 高频大功率半导体模块的制造方法分别采用两层分别采用厚膜工艺形成电阻器或高阻抗元件，以及薄膜工艺以形成精确的电路线或元件。

公开(公告)号：US20050025944A1

公开(公告)日：2005-02-03

申请号：US10925644

申请日：2004-08-24

Applicant: Minoru Ogawa ,  Masahiro Izumi ,  Shigeyasu Itoh ,  Shingetsu Yamada ,  Shuuji Suzuki ,  Hiroo Kurosaki

Inventor： Minoru Ogawa ,  Masahiro Izumi ,  Shigeyasu Itoh ,  Shingetsu Yamada ,  Shuuji Suzuki ,  Hiroo Kurosaki

IPC: C08J5/18 ,  C08L71/10 ,  C08L79/08 ,  H01L23/12 ,  H01L23/14 ,  H05K1/03 ,  H05K1/09 ,  H05K3/04 ,  H05K3/10 ,  H05K3/20 ,  H05K3/22 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00 ,  B32B15/08

CPC classification number: H05K3/4632 ,  H01L2224/16 ,  H01L2224/83192 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/09701 ,  H05K1/0353 ,  H05K1/0373 ,  H05K1/095 ,  H05K3/041 ,  H05K3/045 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2203/0108 ,  H05K2203/065 ,  Y02P20/582 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T428/24917 ,  Y10T428/249994

Abstract: A multilayer wiring board with a high degree of heat resistance, which is capable of low temperature fusion without the occurrence of resin flow, enables high precision, finely detailed conductive wiring, can be ideally applied to low volume high mix manufacturing configurations, and also has little impact on the environment is provided, together with a semiconductor device mounting board using such a multilayer wiring board, and a method of manufacturing such a multilayer wiring board. In the multilayer wiring board, grooves for forming a wiring circuit and via holes are formed in an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, a metallic foil is embedded within the grooves so that the surface of the foil protrudes to the surface of the insulating substrate, and a conductive material formed by curing a conductive paste is used for filling the via holes.

Abstract translation: 具有耐热性高的多层布线基板，其能够低温熔融而不发生树脂流动，能够实现高精度，细致的导电布线，理想地应用于低体积高混合物制造配置，并且还具有 与使用这种多层布线板的半导体装置安装板一起提供对环境的影响很小，以及制造这种多层布线板的方法。 在多层布线板中，形成布线电路和通孔的槽形成在由包含结晶熔融峰值温度至少为260℃的聚芳基酮树脂的热塑性树脂组合物形成的绝缘基板和无定形聚醚酰亚胺树脂中 主要成分，金属箔被嵌入槽内，使得箔的表面突出到绝缘基板的表面，并且通过固化导电膏形成的导电材料用于填充通孔。