中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

129 records (took 0.015 seconds)

    MULTI-LAYER CIRCUIT SUBSTRATE MANUFACTURING METHOD AND MULTI-LAYER CIRCUIT SUBSTRATE
    31.
    发明申请
    MULTI-LAYER CIRCUIT SUBSTRATE MANUFACTURING METHOD AND MULTI-LAYER CIRCUIT SUBSTRATE 审中-公开
    多层电路基板制造方法及多层电路基板

    公开(公告)号：US20090032285A1

    公开(公告)日：2009-02-05

    申请号：US11814698

    申请日：2005-01-27

    Applicant: Yoji Ueda ,  Susumu Matsuoka ,  Rikiya Okimoto ,  Shozo Ochi ,  Satoru Tomekawa

    Inventor： Yoji Ueda ,  Susumu Matsuoka ,  Rikiya Okimoto ,  Shozo Ochi ,  Satoru Tomekawa

    IPC: H05K3/46 ,  H05K1/14 ,  H05K1/00

    CPC classification number: H05K1/024 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0355 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/1461 ,  Y10T428/24843

    Abstract: A method of manufacturing a multilayered circuit board includes the steps of: manufacturing a laminated body by laminating a prepreg of a predetermined thickness on at least one surface of a double-sided circuit board having a grounding link and a signal wiring patterned on both surfaces thereof; and applying heat and pressure to the laminated body and completing a layered structure in which the signal wiring is laid inside the prepreg at a boundary between the double-sided circuit board and the prepreg, wherein prepreg sheets of a predetermined thickness are used in a completed layered structure so that a thickness of a prepreg of the double-sided circuit board is smaller than a distance between a surface of the prepreg on a side not opposed to the double-sided circuit board and the signal wiring laid inside the prepreg.

    Abstract translation: 一种制造多层电路板的方法包括以下步骤：通过在具有接地链路的双面电路板和在其两个表面上图案化的信号布线的至少一个表面层压预定厚度的预浸料来制造层压体 ; 并且对层压体施加热和压力，并且完成在双面电路板和预浸料坯之间的边界处将信号布线放置在预浸料坯内部的层状结构，其中预定厚度的预浸料片材用于完成 使得双面电路板的预浸料坯的厚度小于与双面电路板不相对的一侧上的预浸料坯的表面与布置在预浸料坯内部的信号线之间的距离。

    Multi-layer circuit board having signal, ground and power layers
    32.
    再颁专利
    Multi-layer circuit board having signal, ground and power layers 有权
    具有信号，接地和电源层的多层电路板

    公开(公告)号：USRE40068E1

    公开(公告)日：2008-02-19

    申请号：US10888966

    申请日：2004-07-09

    Applicant: Yu-Chiang Cheng

    Inventor： Yu-Chiang Cheng

    IPC: H05K1/03

    CPC classification number: H05K1/024 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/4688 ,  H05K2201/0145 ,  H05K2201/0191 ,  H05K2201/09327

    Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates; first, second, third, fourth and fifth signal wiring layers; first and second ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 6.5 mil. Each of the second, fourth and sixth insulating substrates has a thickness ranging from 3 to 9 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 23 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the first ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the second ground wiring layer and the power wiring layer. The fifth signal wiring layer has a fifth resistance with respect to the second ground wiring layer. The first, second, third, fourth and fifth resistances are within the range of 49.5 to 60.5 ohms.

    Abstract translation: 多层电路板包括第一，第二，第三，第四，第五，第六和第七绝缘基板; 第一，第二，第三，第四和第五信号布线层; 第一和第二接地布线层; 和电力布线层。 第一和第七绝缘基板中的每一个具有2.5至6.5密耳的厚度。 第二，第四和第六绝缘基板中的每一个具有3至9密耳的厚度。 第三和第五绝缘基板中的每一个具有3至23密耳的厚度。 第一信号布线层相对于第一接地布线层具有第一电阻。 第二信号布线层相对于第一接地布线层和电源布线层具有第二电阻。 第三信号布线层相对于第一接地布线层和电源布线层具有第三电阻。 第四信号布线层相对于第二接地布线层和电源布线层具有第四电阻。 第五信号布线层相对于第二接地布线层具有第五电阻。 第一，第二，第三，第四和第五电阻在49.5至60.5欧姆的范围内。

    Techniques for distributing current in a backplane assembly and methods for making the same
    34.
    发明授权
    Techniques for distributing current in a backplane assembly and methods for making the same 有权
    在背板组件中分配电流的技术及其制造方法

    公开(公告)号：US07154761B1

    公开(公告)日：2006-12-26

    申请号：US10778418

    申请日：2004-02-13

    Applicant: Sergio Camerlo ,  Irfan Elahi

    Inventor： Sergio Camerlo ,  Irfan Elahi

    IPC: H01R12/16

    CPC classification number: H05K1/141 ,  H01R12/523 ,  H05K1/0263 ,  H05K3/222 ,  H05K3/3447 ,  H05K2201/044 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/10303

    Abstract: A backplane assembly includes a main backplane having a first power conductor, a backplane strip having a second power conductor, and connecting members disposed between the main backplane and the backplane strip. The connecting members hold the backplane strip in a fixed position relative to the main backplane and electrically connect the first power conductor and the second power conductor. In one arrangement, the connecting members include source standoffs which extend from a source area of the main backplane to the backplane strip, and target standoffs which extend from a target area of the main backplane to the backplane strip. The source and target standoffs and the second power conductor provide a current path which increases current carrying capacity from the source area to the target area above that provided by the first power conductor alone. Thus, the backplane assembly is well-provisioned for distributing high currents to circuit boards.

    Abstract translation: 背板组件包括具有第一电源导体的主背板，具有第二电源导体的底板条和设置在主背板和背板条之间的连接构件。 连接构件将背板条相对于主底板固定在固定位置，并电连接第一电力导体和第二电力导体。 在一种布置中，连接构件包括从主背板的源区域延伸到背板条的源支座以及从主底板的目标区域延伸到底板条的目标支架。 源和目标支座和第二电力导体提供电流路径，其增加从源区域到目标区域的电流承载能力，高于由第一电力导体单独提供的电流路径。 因此，背板组件设计良好，用于将高电流分​​配给电路板。

    Reconfigurable multilayer printed circuit board
    37.
    发明申请
    Reconfigurable multilayer printed circuit board 有权
    可重构多层印刷电路板

    公开(公告)号：US20030196832A1

    公开(公告)日：2003-10-23

    申请号：US10125246

    申请日：2002-04-18

    Inventor： Melvin Peterson

    IPC: H05K001/03

    CPC classification number: H05K1/0218 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/0005 ,  H05K2201/0723 ,  H05K2201/09327 ,  H01L2924/00

    Abstract: The present invention is a reconfigurable substrate which includes at least one signal line layer stack. Each signal line layer stack is defined to include two substantially parallel insulating layers and a signal line layer interposed between the two insulating layers and substantially parallel to the insulating layers. The substrate includes at least one conductive isolation layer adjacent to at least one signal line layer stack and substantially parallel to the at least one signal line layer stack. The substrate is reconfigurable to different performance levels by adding or removing at least one conductive isolation layer.

    Abstract translation: 本发明是一种可重构衬底，其包括至少一个信号线层堆叠。 每个信号线层堆叠被限定为包括两个基本上平行的绝缘层和插入在两个绝缘层之间并且基本上平行于绝缘层的信号线层。 衬底包括与至少一个信号线层堆叠相邻并且基本上平行于至少一个信号线层堆叠的至少一个导电隔离层。 通过添加或去除至少一个导电隔离层，衬底可重新配置成不同的性能水平。

    Multi-layer circuit board
    38.
    发明授权
    Multi-layer circuit board 有权
    多层电路板

    公开(公告)号：US06326557B1

    公开(公告)日：2001-12-04

    申请号：US09799900

    申请日：2001-03-06

    Applicant: Yu-Chiang Cheng

    Inventor： Yu-Chiang Cheng

    IPC: H05K103

    CPC classification number: H05K1/024 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/4611 ,  H05K2201/0145 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/09327

    Abstract: A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth wiring layers, a ground wiring layer and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.6 mm. Each of the first and fifth insulating substrates has a thickness of 5.7±0.285 mil. Each of the second and fourth insulating substrates has a thickness of 8±0.4 mil. The third insulating substrate has a thickness of 24.6±1.23 mil. The first signal wiring layer has a first resistance with respect to the ground wiring layer. The second signal wiring layer has a second resistance with respect to the ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the power wiring layer. The first, second, third and fourth resistances are within the range of 49.5 to 60.5 ohms.

    Abstract translation: 多层电路板包括第一，第二，第三，第四和第五绝缘基板，第一，第二，第三和第四布线层，接地布线层和电力布线层。 绝缘基板和布线层彼此压接，形成约1.6mm厚度的电路板。 第一和第五绝缘基板中的每一个具有5.7±0.285密耳的厚度。 第二绝缘基板和第四绝缘基板中的每一个具有8±0.4密耳的厚度。 第三绝缘基板的厚度为24.6±123密耳。 第一信号布线层相对于接地布线层具有第一电阻。 第二信号布线层相对于接地布线层和电力布线层具有第二电阻。 第三信号布线层相对于接地布线层和电源布线层具有第三电阻。 第四信号布线层相对于电力布线层具有第四电阻。 第一，第二，第三和第四电阻在49.5至60.5欧姆的范围内。

    Multi-layer printed-wiring boards with inner power and ground layers
    40.
    发明授权
    Multi-layer printed-wiring boards with inner power and ground layers 有权
    具有内部电源和接地层的多层印刷电路板

    公开(公告)号：US06175088B1

    公开(公告)日：2001-01-16

    申请号：US09166828

    申请日：1998-10-05

    Applicant: Sean M. Saccocio

    Inventor： Sean M. Saccocio

    IPC: H01R909

    CPC classification number: H05K1/113 ,  H01R12/523 ,  H05K1/0298 ,  H05K1/115 ,  H05K2201/09227 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/09627

    Abstract: In a multi-layer printed-wiring board (100) the ground and power conductor-bearing layers (102 and 103) are placed immediately (without intermediancy of other conductive layers) below the outer surface conductor-bearing layers (101) and are connected to the outer surface layers by micro-vias (110 and 111) that do not extend beyond the ground and power layers, whereby the micro-vias avoid causing trace-routing blockages on lower, signal-routing, layers (104). The surface layers define traces for static and infrequently-changing signals. One or both of the ground and power layers define double pads (203) each comprising a pair of normal pads (204-205) interconnected by a short trace (206). One single pad of each pair is connected by a micro-via to a corresponding pad (202) on an outer surface layer, which also typically has a lead (201) of a component (200) soldered thereto or serves as a testpad. The other single pad of each pair is connected by a buried through-hole via (207) to pads (208) on the lower, signal-routing, layers. This removes the double pads from the outer surface layer and thus reduces trace-routing blockages on the outer surface layer, and at the same time solves the problem of connecting micro-vias to through-hole vias.

    Abstract translation: 在多层印刷电路板（100）中，地面和电力导体承载层（102和103）被立即（没有其他导电层的介入）放置在外表面导体承载层（101）下方并被连接 通过不延伸超过接地层和功率层的微通孔（110和111）到外表面层，由此微通孔避免在较低信号路由层（104）上引起轨迹路由阻塞。 表面层为静态和不频繁变化的信号定义轨迹。 接地层和功率层中的一个或两个限定双重衬垫（203），每个衬垫包括通过短迹（206）互连的一对正常焊盘（204-205）。 每对的一个单个焊盘通过微通孔连接到外表面层上的相应的焊盘（202），外表面层通常还具有焊接到其上的部件（200）的引线（201）或用作测试板。 每对的另一个单个焊盘通过埋入通孔（207）连接到较低信号路由层上的焊盘（208）。 这从外表面层去除双垫，从而减少外表面层上的迹线路由阻塞，同时解决了将微通孔连接到通孔通孔的问题。

Patent Agency Ranking