公开(公告)号：US20040090760A1

公开(公告)日：2004-05-13

申请号：US10239732

申请日：2002-11-13

Inventor： Walter Schmidt

IPC: H05K001/11 ,  H05K001/14

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  H01L2924/00

Abstract: The electrical connecting element includes an essentially stiff core, essentially mechanically stiff and printed circuit boards and/or high density interconnects with conductor paths serving as interconnects. The core includes two parts (1, 3) that can be fixed to each other. Between the two parts, a cavity (101) can be formed. Components (103) producing a lot of heat or requiring protection from environmental influences can be placed in the cavity.

Abstract translation: 电连接元件包括基本上刚性的芯，基本上机械刚性的印刷电路板和/或具有用作互连的导体路径的高密度互连。 核心包括可以彼此固定的两个部分（1,3）。 在两个部分之间，可以形成空腔（101）。 产生大量热量或需要防止环境影响的部件（103）可以放置在空腔中。

公开(公告)号：US06734557B2

公开(公告)日：2004-05-11

申请号：US10369760

申请日：2003-02-21

Applicant: Kiyomi Taniguchi ,  Hisashige Nishida

Inventor： Kiyomi Taniguchi ,  Hisashige Nishida

IPC: H01L2348

CPC classification number: H05K3/3452 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/113 ,  H05K2201/09527 ,  H05K2201/0989 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device comprising: a substrate; first and second interconnection patterns respectively provided on upper and lower surfaces of the substrate; a through-hole electrode extending through the substrate for electrically connecting the first and second interconnection patterns; a semiconductor chip provided on the upper surface of the substrate and electrically connected to the first interconnection pattern; and a resist film covering the second interconnection pattern; the second interconnection pattern comprising a generally round land and a lead interconnection portion extending from the land, the resist film having an opening formed therein for exposing the entire land, the opening having a curved edge surrounding a peripheral edge of the land and a linear edge linearly extending along a boundary between the land and the lead interconnection portion, the exposed land having a solder ball as an external terminal thereon.

Abstract translation: 一种半导体器件，包括：衬底; 分别设置在基板的上表面和下表面上的第一和第二互连图案; 延伸穿过所述基板的用于电连接所述第一和第二互连图案的通孔电极; 设置在所述基板的上表面并电连接到所述第一互连图案的半导体芯片; 以及覆盖所述第二互连图案的抗蚀剂膜; 所述第二互连图案包括大致圆形的平台和从所述焊盘延伸的引线互连部分，所述抗蚀剂膜具有形成在其中的开口，用于暴露所述整个焊盘，所述开口具有围绕所述焊盘边缘的弯曲边缘， 沿着焊盘和引线互连部分之间的边界线性延伸，暴露的焊盘在其上具有焊球作为外部端子。

公开(公告)号：US20030168255A1

公开(公告)日：2003-09-11

申请号：US10384658

申请日：2003-03-11

Applicant: LG ELECTRONICS INC.

Inventor： Dock-Heung Kim ,  Yong-Il Kim

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K3/4652 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/0097 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913

Abstract: A multi-layer printed circuit board on which insulation resin layers and circuit pattern layers are alternatively stacked to form multiple layers, including: an insulation resin layer; a circuit pattern formed at the upper surface of the insulation resin layer; a blind via hole formed penetrating the insulation resin layer and the circuit pattern; a plated layer formed at the upper surface of the circuit pattern, at the inner wall face and the bottom of the blind via hole; an inner lead bump pad formed at the surface of the plated layer which is exposed to the lower surface of the insulation resin layer; and an outer lead bump pad formed on the circuit pattern which is formed at the upper surface of the insulation resin layer, whereby the problem of defective attachment of a bump due to a void present in a blind via hole is eliminated.

公开(公告)号：US06418615B1

公开(公告)日：2002-07-16

申请号：US09523149

申请日：2000-03-10

Applicant: Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

Inventor： Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

IPC: H01K310

CPC classification number: H05K3/4682 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/113 ,  H05K3/007 ,  H05K3/045 ,  H05K3/108 ,  H05K3/20 ,  H05K3/205 ,  H05K3/388 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0384 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49345

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract translation: 一种多层结构的基板，具有多组绝缘层和布线层，并且具有用于安装半导体元件的一个面和将要设置外部连接端子的另一个面，用于安装半导体的面 元件设置有要接合到半导体元件的电极端子的焊盘，另一个面设置有焊接到外部连接端子，例如由焊球形成的端子，并且两个布线层 绝缘层的侧面通过穿过绝缘层的通孔相互连接，其中要结合到半导体元件的电极端子的焊盘的表面是平坦的并且在同一平面中。 还公开了制造这种多层基板的方法。

公开(公告)号：US20010027875A1

公开(公告)日：2001-10-11

申请号：US09832193

申请日：2001-04-11

Inventor： Dock-Heung Kim ,  Yong-Il Kim

IPC: H05K001/03

CPC classification number: H05K3/4652 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/0097 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913

Abstract: A multi-layer printed circuit board on which insulation resin layers and circuit pattern layers are alternatively stacked to form multiple layers, including: an insulation resin layer; a circuit pattern formed at the upper surface of the insulation resin layer; a blind via hole formed penetrating the insulation resin layer and the circuit pattern; a plated layer formed at the upper surface of the circuit pattern, at the inner wall face and the bottom of the blind via hole; an inner lead bump pad formed at the surface of the plated layer which is exposed to the lower surface of the insulation resin layer; and an outer lead bump pad formed on the circuit pattern which is formed at the upper surface of the insulation resin layer, whereby the problem of defective attachment of a bump due to a void present in a blind via hole is eliminated.

Abstract translation: 一种多层印刷电路板，其上绝缘树脂层和电路图案层交替堆叠形成多层，包括：绝缘树脂层; 形成在所述绝缘树脂层的上表面的电路图案; 穿过绝缘树脂层和电路图案的盲通孔; 在电路图案的上表面形成在盲通孔的内壁面和底部的镀层; 内部引线凸块焊盘，其形成在所述绝缘树脂层的下表面的所述镀层的表面， 以及形成在电路图案上的外部引线凸块焊盘，其形成在绝缘树脂层的上表面处，由此消除了由于存在于盲孔中的空隙而引起的凸起不良的附着问题。

公开(公告)号：US5879787A

公开(公告)日：1999-03-09

申请号：US747171

申请日：1996-11-08

Applicant: William George Petefish

Inventor： William George Petefish

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K1/00 ,  H05K1/05 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/44 ,  B32B9/00

CPC classification number: H05K1/113 ,  H01L21/486 ,  H01L23/49827 ,  H05K3/421 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K1/056 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09827 ,  H05K2203/1147 ,  H05K3/0035 ,  H05K3/427 ,  H05K3/445 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A method of making a laminated structure includes forming a first lamination having first and second conductive layers having inner and outer surfaces and being spaced apart by a dielectric layer, drilling through the first conductive layer and dielectric layer to form a blind via having a bottom coexistent with the inner surface of the second conductive layer, plating the blind via with a conductive material, and patterning the second conductive layer to form at least one contact pad over the blind via.

Abstract translation: 制造叠层结构的方法包括形成具有第一和第二导电层的第一和第二层的第一层和第二层，所述第一和第二导电层具有内表面和外表面并且被电介质层隔开，穿过第一导电层和介电层，以形成具有底部共存的盲孔 与第二导电层的内表面，用导电材料电镀盲孔，并且图案化第二导电层以在盲孔上形成至少一个接触垫。

公开(公告)号：US5258094A

公开(公告)日：1993-11-02

申请号：US942746

申请日：1992-09-09

Applicant: Seiji Furui ,  Ryo Maniwa ,  Kiminori Ishido ,  Keisuke Okada

Inventor： Seiji Furui ,  Ryo Maniwa ,  Kiminori Ishido ,  Keisuke Okada

IPC: H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  B44C1/22 ,  B29C37/00 ,  C23F1/00

CPC classification number: H05K3/4614 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09536 ,  H05K2203/063 ,  H05K2203/1572 ,  H05K3/0023 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K3/4647 ,  Y10T29/49165

Abstract: A multilayered board is formed by applying a photosensitive insulating resin layer on a laminated plate on which via holes and a circuit pattern are formed, followed by the formation of photoviaholes through the photoprinting method, plating and etching. Then, the multilayered board is adhered to another multilayered board prepared in the same manner through a prepreg layer and a conductive paste while applying heat and pressure to give a multilayer printed wiring board. According to this method, electrical connections between the conductive layer of the upper-most layer and the inner conductive layers, between the inner conductive layers, and between the lower-most conductive layer and the inner conductive layers can be achieved through the photoviaholes and the conductive paste. Therefore, it is not necessary to form through-holes for the electrical connection therebetween. The multilayer printed wiring boards can be substantially improved in the number of layers and wiring density thereof.

Abstract translation: 通过在形成有通孔和电路图案的层叠板上施加感光绝缘树脂层，然后通过照相印刷法，电镀和蚀刻形成光电导孔，形成多层板。 然后，通过预浸料层和导电性浆料，通过加热和加压将多层板粘贴到以相同方式制备的另一多层板上，得到多层印刷线路板。 根据这种方法，可以通过光导孔和光导体层来实现最上层的导电层和内部导电层之间，内部导电层之间以及最下面的导电层与内部导电层之间的电连接 导电胶 因此，不需要形成用于它们之间的电连接的通孔。 多层印刷电路板的层数和布线密度可以大大提高。

公开(公告)号：US20240055744A1

公开(公告)日：2024-02-15

申请号：US18383552

申请日：2023-10-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Nobuo IKEMOTO

IPC: H01P3/08 ,  H05K3/46 ,  H05K1/02 ,  H01P11/00

CPC classification number: H01P3/08 ,  H05K3/46 ,  H05K1/0219 ,  H01P11/003 ,  H05K2201/09527 ,  H05K2201/09609 ,  H05K2201/096

Abstract: A first conductive layer is in contact with a first inter-layer connection conductor and a second inter-layer connection conductor. The first conductive layer has a same composition as the first and second inter-layer connection conductors. At least one first metal foil layer is in contact with a third main surface of the first conductive layer. The at least one first metal foil layer overlaps the first and second inter-layer connection conductors when viewed in a first direction. At least one second metal foil layer overlaps the first and second inter-layer connection conductors when viewed in the first direction, and is electrically connected to the first and second inter-layer connection conductors. The at least one second metal foil layer has a composition different from that of the first conductive layer.

公开(公告)号：US09999129B2

公开(公告)日：2018-06-12

申请号：US12590650

申请日：2009-11-12

Applicant: John S. Guzek ,  Mihir K. Roy ,  Brent M. Roberts

Inventor： John S. Guzek ,  Mihir K. Roy ,  Brent M. Roberts

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/64 ,  H05K1/16 ,  H01L23/00 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/165 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0254 ,  H05K1/0262 ,  H05K1/116 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A microelectronic device comprises a first substrate (110) having a first electrically conductive path (111) therein and a second substrate (120) above the first substrate and having a second electrically conductive path (121) therein, wherein the first electrically conductive path and the second electrically conductive path are electrically connected to each other and form a portion of a current loop (131) of an inductor (130).

公开(公告)号：US09961784B2

公开(公告)日：2018-05-01

申请号：US15475134

申请日：2017-03-31

Applicant: Subtron Technology Co., Ltd.

Inventor： Tzu-Wei Huang

IPC: H05K3/46 ,  H05K3/42 ,  H05K3/00 ,  H05K3/02 ,  H05K1/11 ,  B23K11/11 ,  B32B37/02 ,  B32B37/04 ,  B32B38/10 ,  B32B38/04 ,  B32B37/00 ,  B23K101/42

CPC classification number: H05K3/4682 ,  B23K11/11 ,  B23K2101/42 ,  B32B37/0084 ,  B32B37/02 ,  B32B37/04 ,  B32B38/04 ,  B32B38/10 ,  B32B2038/047 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2311/00 ,  B32B2311/12 ,  B32B2457/00 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/02 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/46 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/1536 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.