公开(公告)号：US20140113415A1

公开(公告)日：2014-04-24

申请号：US13924705

申请日：2013-06-24

Applicant: Samsung Techwin Co., Ltd.

Inventor： Sang-Min LEE

IPC: H01L21/52 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L21/52 ,  H01L23/053 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/12042 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/002 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/09118 ,  H05K2201/09536 ,  H05K2201/09845 ,  H05K2203/0554 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Provided is a method of manufacturing a circuit board. The method includes: preparing a base substrate including a core layer and a first conductive layer that is formed on at least one surface of the core layer and includes an internal circuit pattern; forming a build-up material to cover the first conductive layer; forming in the build-up material at least one cavity through which the core layer and the first conductive layer are exposed; forming a laminated body by curing the build-up material in which the at least one cavity is formed; and forming a second conductive layer including an external circuit pattern on an outer surface of the laminated body.

Abstract translation: 提供一种制造电路板的方法。 该方法包括：制备包括芯层的基底基板和形成在芯层的至少一个表面上并包括内部电路图案的第一导电层; 形成积层材料以覆盖所述第一导电层; 在堆积材料中形成芯层和第一导电层暴露的至少一个空腔; 通过固化形成所述至少一个腔的所述积聚材料来形成层压体; 以及在所述层叠体的外表面上形成包括外部电路图案的第二导电层。

公开(公告)号：US08669480B2

公开(公告)日：2014-03-11

申请号：US12050646

申请日：2008-03-18

Applicant: Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Masakazu Aoyama

IPC: H01R12/04

CPC classification number: H05K3/4691 ,  H05K1/0373 ,  H05K3/0032 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2203/1536

Abstract: A wiring board and method of forming a wiring board including a first substrate, a second substrate having a smaller mounting area than a mounting area of the first substrate, and a base substrate laminated between the first substrate and the second substrate, such that the first substrate extends beyond an edge of the second substrate. An IVH (Interstitial Via Hole) or through hole penetrates the base substrate and vias are formed in at least one of the first substrate or the second substrate.

Abstract translation: 一种布线板以及形成布线板的方法，所述布线板包括第一基板，具有比所述第一基板的安装面积小的安装面积的第二基板以及层叠在所述第一基板和所述第二基板之间的基底基板， 衬底延伸超过第二衬底的边缘。 IVH（间隙通孔）或通孔穿透基底基板，并且通孔形成在第一基板或第二基板中的至少一个中。

公开(公告)号：US20140033146A1

公开(公告)日：2014-01-30

申请号：US14042908

申请日：2013-10-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

公开(公告)号：US08624297B2

公开(公告)日：2014-01-07

申请号：US12579517

申请日：2009-10-15

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L27/10 ,  H01L21/4763

CPC classification number: H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract translation: 集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

公开(公告)号：US08592688B2

公开(公告)日：2013-11-26

申请号：US12649038

申请日：2009-12-29

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/16

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

公开(公告)号：US08580066B2

公开(公告)日：2013-11-12

申请号：US13372088

申请日：2012-02-13

Applicant: Erina Yamada ,  Hironori Sato

Inventor： Erina Yamada ,  Hironori Sato

IPC: B29C65/52 ,  B32B37/02 ,  B32B37/12 ,  B32B38/10 ,  B32B38/04 ,  B32B43/00 ,  C09J5/00

CPC classification number: H05K3/4682 ,  H01L2924/15174 ,  H05K3/0097 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/1536 ,  Y10T156/1056

Abstract: A method for manufacturing a reliable multilayer wiring substrate at a relatively low cost having little or no warpage or distortion is provided. In certain embodiments an insulation core made of an insulation material that is more rigid than that of resin insulation layers is prepared. A through hole is formed through core upper and lower surfaces of the insulation core, and a through hole conductor is formed therein. A plate-like substrate is prepared, and resin insulation layers and at least one conductor layer are laminated on the substrate to form a first buildup layer. The insulation core is laminated on the first buildup layer so as to electrically connect the conductor layer and the through hole conductor. Resin insulation layers and at least one conductor layer are then laminated on the insulation core. Lastly, the substrate is separated from the first buildup layer to yield a multilayer wiring substrate.

Abstract translation: 提供了具有很少或没有翘曲或变形的成本较低的可靠的多层布线基板的制造方法。 在某些实施例中，制备由绝缘材料制成的绝缘芯，该绝缘芯比树脂绝缘层更硬。 通过绝缘芯的中心和下表面形成通孔，并在其中形成通孔导体。 制备板状基板，在基板上层叠树脂绝缘层和至少一层导体层，形成第一累积层。 绝缘芯层压在第一堆积层上，以电连接导体层和通孔导体。 树脂绝缘层和至少一个导体层然后层压在绝缘芯上。 最后，将基板与第一堆积层分离，得到多层布线基板。

公开(公告)号：US20130248234A1

公开(公告)日：2013-09-26

申请号：US13872650

申请日：2013-04-29

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/18

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：USRE44251E1

公开(公告)日：2013-06-04

申请号：US10839813

申请日：2004-05-06

Applicant: Motoo Asai ,  Yoichiro Kawamura ,  Yoji Mori

Inventor： Motoo Asai ,  Yoichiro Kawamura ,  Yoji Mori

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R12/523 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/114 ,  H05K3/184 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0212 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09727 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: A board for mounting electronic circuit parts includes a first connection terminal group including a plurality of connection terminals densely formed on the top surface of a substrate having through holes formed therein, and a second connection terminal group including a plurality of connection terminals formed at at least the peripheral portion of a back surface of the substrate. The first connection terminal group is connected to the second connection terminal group by way of the through holes. A build-up multilayer interconnection layer having via holes is formed on the top surface of the substrate, so that the first connection terminal group is connected to the second connection terminal group through the build-up multilayer interconnection layer and the through holes. According to another aspect, each signal line on the top surface of the build-up multilayer interconnection layer comprises a plurality of wiring patterns having different widths and a taper-shaped pattern that connects those wiring patterns together and whose width continuously changes. Each signal line has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density.

公开(公告)号：US08440917B2

公开(公告)日：2013-05-14

申请号：US11942061

申请日：2007-11-19

Applicant: Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

Inventor： Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0233 ,  H05K1/112 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09536 ,  H05K2201/096

Abstract: A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Abstract translation: 一种用于涂覆电镀通孔（PTH）的方法，系统和装置，以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。 迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

公开(公告)号：US20130075148A1

公开(公告)日：2013-03-28

申请号：US13426892

申请日：2012-03-22

Applicant: Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

Inventor： Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0233 ,  H05K1/112 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09536 ,  H05K2201/096

Abstract: A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Abstract translation: 一种具有电镀通孔（PTH）的器件和/或设备，其被涂覆以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。 迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。