公开(公告)号：US09226388B2

公开(公告)日：2015-12-29

申请号：US13955474

申请日：2013-07-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang-Kyung Lee ,  Hee-Kyoung Lee ,  Dong-Hwan Lee ,  Kyung-Sang Lim

IPC: H05K9/00 ,  H05K1/03 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0242 ,  H05K1/0219 ,  H05K1/0233 ,  H05K2201/086 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/0979

Abstract: A printed circuit board disclosed. One embodiment of the present invention provides a printed circuit board that includes: an insulation layer having multiple layers of circuit wirings formed therein; a via formed along a perimeter of the insulation layer and configured for connecting circuit wirings formed on different layers of the insulation layer, the via being formed in such a way that an inside thereof is hollow; and an electromagnetic wave absorbing part contained in the via.

Abstract translation: 公开了印刷电路板。 本发明的一个实施例提供了一种印刷电路板，其包括：绝缘层，其中形成有多层电路布线; 沿绝缘层的周边形成的通孔，其被构造用于连接形成在绝缘层的不同层上的电路布线，所述通孔以使其内部为中空的方式形成; 以及包含在通孔中的电磁波吸收部。

公开(公告)号：US20150296624A1

公开(公告)日：2015-10-15

申请号：US14438660

申请日：2013-05-09

Applicant: LG INNOTEK CO., LTD.

Inventor： Yun Ho An ,  Won Suk Jung ,  Ran Kim ,  Sung Soo Park ,  Young Joon Son ,  Sang Myung Lee ,  Woo Young Lee ,  Joon Wook Han

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/09136 ,  H05K2201/095 ,  H05K2201/0959 ,  H05K2201/10636 ,  H05K2203/0191 ,  Y02P70/611

Abstract: A printed circuit board for mounting a chip includes: a core layer including a chip mounting cavity; a chip mounted into the chip mounting cavity; a first insulating material layer filled in a space between the chip mounting cavity and the chip; and a second insulating material layer laminated on one surface of the core layer.

Abstract translation: 用于安装芯片的印刷电路板包括：芯层，包括芯片安装腔; 芯片安装在芯片安装腔中; 填充在芯片安装腔和芯片之间的空间中的第一绝缘材料层; 以及层叠在芯层的一个表面上的第二绝缘材料层。

公开(公告)号：US09107314B2

公开(公告)日：2015-08-11

申请号：US13799221

申请日：2013-03-13

Applicant: FUJITSU LIMITED

Inventor： Hideaki Yoshimura

IPC: H01K3/10 ,  H05K1/11 ,  H05K3/40 ,  H05K3/44 ,  H05K3/46 ,  G01R31/28 ,  H05K3/42

CPC classification number: H05K1/115 ,  G01R31/2889 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/4038 ,  H05K3/425 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: A method of manufacturing a wiring board includes: forming an outer through hole in a core substrate; filling the outer through hole with an insulation resin; forming a first conductive layer on a surface of the insulation resin at a portion where a core connecting via is formed; forming a land around the first conductive layer; laminating the wiring layer on the core substrate after the forming of the first conductive layer and the forming of the land; forming an inner through hole having a smaller diameter than that of the outer through hole and penetrating through the core substrate and the wiring layer so as to penetrate through the insulation resin; and coating a first conductive film on an inner wall surface of the inner through hole, in which the core substrate and the first conductive film are electrically connected through the first conductive layer and the land.

Abstract translation: 制造布线板的方法包括：在芯基板中形成外通孔; 用绝缘树脂填充外部通孔; 在形成芯连接通孔的部分上在绝缘树脂的表面上形成第一导电层; 形成围绕所述第一导电层的区域; 在形成第一导电层并形成焊盘之后，在芯基板上层叠布线层; 形成直径小于所述外通孔直径的内通孔，穿过所述芯基板和所述布线层以贯穿所述绝缘树脂; 并且在内部通孔的内壁表面上涂覆第一导电膜，其中芯基板和第一导电膜通过第一导电层和焊盘电连接。

公开(公告)号：US09099458B2

公开(公告)日：2015-08-04

申请号：US13539480

申请日：2012-07-01

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K1/11 ,  H05K1/09 ,  H01L23/498 ,  H05K3/46 ,  H05K1/02

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 镀层通孔着色包括蚀刻图案。

公开(公告)号：US20150102510A1

公开(公告)日：2015-04-16

申请号：US14512754

申请日：2014-10-13

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Wataru Kaneda ,  Noriyoshi Shimizu ,  Akio Rokugawa ,  Kaori Yokota

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H01L23/00

CPC classification number: H05K1/18 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16054 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/12042 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/043 ,  H05K3/4007 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4673 ,  H05K2201/0209 ,  H05K2201/0909 ,  H05K2201/09145 ,  H05K2201/09154 ,  H05K2201/0959 ,  H05K2201/2072 ,  H05K2203/025 ,  H05K2203/0773 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A wiring board includes a first insulating layer containing a thermosetting resin, a first wiring layer stacked on an upper surface of the first insulating layer, a second insulating layer stacked on the upper surface of the first insulating layer, a second wiring layer stacked on an upper surface of the second insulating layer, and a third insulating layer stacked on the upper surface of the second insulating layer. The second and third insulating layers contain a first photosensitive resin. An outer side surface of the second insulating layer is flush with an outer side surface of the first insulating layer. An outer side surface of the third insulating layer is located inside the outer side surface of the second insulating layer in a plan view. The upper surface of the second insulating layer connecting to the outer side surface thereof is exposed from the third insulating layer.

Abstract translation: 布线基板包括含有热固性树脂的第一绝缘层，堆叠在第一绝缘层的上表面上的第一布线层，堆叠在第一绝缘层的上表面上的第二绝缘层，堆叠在第一绝缘层上的第二布线层 第二绝缘层的上表面和堆叠在第二绝缘层的上表面上的第三绝缘层。 第二和第三绝缘层包含第一感光树脂。 第二绝缘层的外侧表面与第一绝缘层的外侧表面齐平。 第三绝缘层的外侧表面在平面图中位于第二绝缘层的外侧表面内。 连接到其外侧表面的第二绝缘层的上表面从第三绝缘层露出。

公开(公告)号：US08908383B1

公开(公告)日：2014-12-09

申请号：US13476923

申请日：2012-05-21

Applicant: Tarak A. Railkar ,  Paul D. Bantz

Inventor： Tarak A. Railkar ,  Paul D. Bantz

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0206 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2201/10098

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of thermal via structures with surface features. In some embodiments the surface features may have dimensions greater than approximately one micron. The thermal via structures may be incorporated into a substrate of an integrated circuit device. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了具有表面特征的热通孔结构的装置，方法和系统。 在一些实施例中，表面特征可具有大于约1微米的尺寸。 热通孔结构可以结合到集成电路器件的衬底中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08866026B2

公开(公告)日：2014-10-21

申请号：US13569826

申请日：2012-08-08

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K1/11 ,  H05K1/09 ,  H05K3/46 ,  H01L23/498 ,  H05K1/02

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括厚度基本为3μm的板状通孔着落。 镀层通孔着色包括蚀刻图案和铜顶表面。

公开(公告)号：US20140246223A1

公开(公告)日：2014-09-04

申请号：US14193462

申请日：2014-02-28

Applicant: Advanced Micro Devices (Shanghai) Co., Ltd.

Inventor： I-Tseng Lee ,  Yu-Ling Hsieh

IPC: H05K1/02

CPC classification number: H01L23/13 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/01078 ,  H05K1/024 ,  H05K1/036 ,  H05K3/0052 ,  H05K3/0061 ,  H05K3/3452 ,  H05K2201/0209 ,  H05K2201/0959 ,  H05K2201/10674 ,  H01L2924/00

Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.

Abstract translation: 本发明涉及一种包括堆积物和设置在积聚物上的阻焊层的基材。 阻焊层具有背离堆积物的上表面。 阻焊层在其上表面具有多个槽。 阻焊层的凹槽可以更好地消除或减轻由热引起的大的阻焊剂区域上积累的应力和/或材料的基板的热膨胀失配系数，从而可以防止和减少基板或封装的翘曲。

公开(公告)号：US08822839B2

公开(公告)日：2014-09-02

申请号：US13307213

申请日：2011-11-30

Applicant: Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

Inventor： Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core substrate, lower interlayer resin insulating layers formed on the surfaces of the core substrate, respectively, through-hole conductors formed in penetrating holes penetrating through the core substrate and the lower interlayer resin insulating layers, conductor circuits formed on the lower interlayer resin insulating layers, respectively, upper interlayer resin insulating layers formed on the conductor circuits and the lower interlayer resin insulating layers, respectively and via hole conductors formed in the upper interlayer resin insulating layers and positioned on the through-hole conductors, respectively.

Abstract translation: 一种多层印刷电路板，包括芯基板，分别形成在芯基板的表面上的下层层间树脂绝缘层，形成在穿透芯基板的穿透孔中的通孔导体和下层间树脂绝缘层，导体 形成在下层树脂绝缘层上的电路分别形成在导体电路和下层间树脂绝缘层上的上层间树脂绝缘层和分别形成在上层间树脂绝缘层中并位于通孔上的通孔导体 导体。

公开(公告)号：US08800143B2

公开(公告)日：2014-08-12

申请号：US13156715

申请日：2011-06-09

Applicant: Youhong Wu

Inventor： Youhong Wu

IPC: H01K3/10

CPC classification number: H05K1/115 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a multi-layer printed wiring board including forming a core substrate, forming a first interlayer insulation layer over the core substrate, forming a first filled via in the first interlayer insulation layer, the first filled via having a bottom portion having a first diameter, forming a second interlayer insulation layer over the first interlayer insulation layer, and forming a second filled via in the second interlayer insulation layer, the second filled via having a bottom portion having a second diameter smaller than the first diameter.

Abstract translation: 一种制造多层印刷布线板的方法，包括形成芯基板，在芯基板上形成第一层间绝缘层，在第一层间绝缘层中形成第一填充通孔，第一填充通孔具有底部， 在所述第一层间绝缘层上形成第二层间绝缘层，在所述第二层间绝缘层中形成第二填充通孔，所述第二填充通孔具有第二直径小于所述第一直径的第二直径。