公开(公告)号：US20140298825A1

公开(公告)日：2014-10-09

申请号：US14247870

申请日：2014-04-08

Applicant: Harman Becker Automotive Systems GmbH

Inventor： Valod NOSHADI

IPC: H05K7/20

CPC classification number: H05K7/205 ,  H01L35/32 ,  H05K1/0201 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/16 ,  H05K2201/09672 ,  H05K2201/10219

Abstract: A circuit board is provided that includes at least one Peltier heat pump device with at least one pair of semiconductor members arranged thermally in parallel and electrically in series. The at least one pair of semiconductor members is at least partially embedded in the circuit board.

Abstract translation: 提供了一种电路板，其包括至少一个珀尔帖热泵装置，其具有并联热电并串联电连接的至少一对半导体部件。 至少一对半导体构件至少部分地嵌入电路板中。

公开(公告)号：US20140273638A1

公开(公告)日：2014-09-18

申请号：US14215817

申请日：2014-03-17

Applicant: Panduit Corp.

Inventor： Joshua A. Valenti ,  Moulik Shah ,  Ronald L. Tellas ,  Robert E. Fransen ,  Satish I. Patel ,  Tse-Yu Lin

IPC: H01R13/6466

CPC classification number: H01R13/6466 ,  H01R24/64 ,  H01R2201/04 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  H05K2201/10303

Abstract: The present invention generally relates to the field of network communications, and more specifically to networks for crosstalk reduction/compensation and communication connectors which employ such networks. In an embodiment, the present invention is an RJ45 jack with an orthogonal. compensation network to meet CAT6A or higher performance standard. For the 3:6-4:5 wire-pair combination, the orthogonal compensation network begins in the jack nose (plug interface contact (PIC)) section, and utilizes a flexible printed circuit board in the nose section, split PIC contacts in the rear nose, and circuitry in the rigid printed circuit board to create the orthogonal compensation network.

Abstract translation: 本发明一般涉及网络通信领域，更具体地涉及使用这种网络的用于串扰减少/补偿和通信连接器的网络。 在一个实施例中，本发明是具有正交的RJ45插孔。 补偿网满足CAT6A或更​​高性能标准。 对于3：6-4：5线对组合，正交补偿网络从插孔（插头接口触点（PIC））部分开始，并在鼻部使用柔性印刷电路板，将PIC触点 后鼻和刚性印刷电路板中的电路，以创建正交补偿网络。

公开(公告)号：US20140256190A1

公开(公告)日：2014-09-11

申请号：US14269265

申请日：2014-05-05

Applicant: Panduit Corp.

Inventor： Jack E. Caveney ,  Scott M. Lesniak

IPC: H01R13/66

CPC classification number: H01R4/2416 ,  H01R4/2433 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/665 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10S439/942 ,  Y10T29/49201 ,  Y10T29/49202 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: A network cable jack includes a printed circuit board (PCB) for balancing both inductive and capacitive coupling. Using a PCB allows compact trace paths to be formed without significantly increasing manufacturing costs. By including on each trace path two distinct inductance zones separated by a neutral zone, significant gains in degrees of freedom are achieved for designing PCB trace patterns in which a pair of inductive coupling zones jointly offset the inductive coupling caused by a specification plug and the jack contacts, both in magnitude and phase angle. Further, using distinct inductance zones offers more freedom regarding the placement of capacitive plates for use in capacitance balancing as well as the placement of terminals and insulation displacement contacts. Although the magnitude of a capacitive coupling is determined by the length of the capacitor plates parallel to current carrying traces, the approach allows capacitive and inductive coupling to be balanced independently.

Abstract translation: 网络电缆插孔包括用于平衡电感和电容耦合的印刷电路板（PCB）。 使用PCB可以形成紧凑的轨迹路径，而不会显着增加制造成本。 通过在每个迹线路径上包括两个由中性区域分开的不同的电感区域，实现了自由度的显着增益，用于设计PCB迹线图案，其中一对感应耦合区域共同抵消了由规格插头和插孔引起的感性耦合 触点，幅度和相位角。 此外，使用不同的电感区域可以提供更多的自由度，用于电容平板的放置以及端子和绝缘位移触点的放置。 虽然电容耦合的大小由与载流轨迹平行的电容器板的长度确定，但该方法允许电容和电感耦合独立平衡。

公开(公告)号：US20140210047A1

公开(公告)日：2014-07-31

申请号：US14240453

申请日：2012-05-25

Applicant: Kazunao Tajima ,  Atsuhiko Tanaka

Inventor： Kazunao Tajima ,  Atsuhiko Tanaka

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F2027/2819 ,  H01L23/48 ,  H01L25/0655 ,  H01L2924/0002 ,  H05K1/0239 ,  H05K1/165 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A semiconductor device including: first and second semiconductor chips mounted on a base substrate; a third semiconductor chip, which is mounted on the base substrate, and outputs control signals controlling operations of the first and second semiconductor chips; a first transmission transformer, which is mounted on the base substrate, and has a reception-side terminal connected to the third semiconductor chip and a transmission-side terminal connected to the first semiconductor chip; and a second transmission transformer, which is mounted on the base substrate, and has a reception-side terminal connected to the third semiconductor chip and a transmission-side terminal connected to the second semiconductor chip, wherein the control signals are transmitted from the third semiconductor chip to the first semiconductor chip and the second semiconductor chip individually through the first transmission transformer and the second transmission transformer.

Abstract translation: 一种半导体器件，包括：安装在基底基板上的第一和第二半导体芯片; 第三半导体芯片，其安装在所述基底基板上，并且输出控制所述第一和第二半导体芯片的操作的控制信号; 第一传输变压器，其安装在基底基板上，并且具有连接到第三半导体芯片的接收侧端子和连接到第一半导体芯片的发送侧端子; 以及第二变压器，其安装在所述基底基板上，具有连接到所述第三半导体芯片的接收侧端子和与所述第二半导体芯片连接的发送侧端子，其中，所述控制信号从所述第三半导体 通过第一变速器变压器和第二变速器单独地分别通向第一半导体芯片和第二半导体芯片。

公开(公告)号：US08787030B2

公开(公告)日：2014-07-22

申请号：US13124751

申请日：2009-10-28

Applicant: Akira Oikawa

Inventor： Akira Oikawa

IPC: H05K7/00

CPC classification number: H05K3/4635 ,  H05K1/165 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/09672

Abstract: A multilayer circuit board (1) includes resin bases (101 to 10N) stacked while placing separators (121 to 12N−1) in between, interconnect patterns (111 to 11N) respectively formed on one surface of each of the resin bases (101 to 10N), and electro-conductive bumps (201 to 20N−1) which electrically connect the interconnect patterns (111 to 11N). The resin bases (101 to 10N) and the separators (121 to 12N−1) are heat-bonded, the separators (121 to 12N−1) are composed of a first thermoplastic resin material having a first glass transition temperature, and the resin bases (101 to 10N) are composed of a second thermoplastic resin material having a second glass transition temperature higher than the first glass transition temperature.

Abstract translation: 多层电路板（1）包括在分隔件（121至12N-1）之间堆叠的树脂基座（101至10N），分别形成在每个树脂基座（101至12N-1）的一个表面上的互连图案（111至11N） 10N）和电连接布线图案（111〜11N）的导电凸块（201〜20N-1）。 树脂基（101〜10N）和隔板（121〜12N-1）进行热粘合，隔板（121〜12N-1）由具有第一玻璃化转变温度的第一热塑性树脂材料构成，树脂 碱（101〜10N）由第二玻璃化转变温度高于第一玻璃化转变温度的第二热塑性树脂材料构成。

公开(公告)号：US20140139240A1

公开(公告)日：2014-05-22

申请号：US14128998

申请日：2012-06-20

Applicant: Stefan Burger

Inventor： Stefan Burger

IPC: G01R1/04

CPC classification number: G01R1/0408 ,  H03K17/962 ,  H03K2017/9602 ,  H03K2217/960765 ,  H03K2217/960775 ,  H05K1/162 ,  H05K2201/0919 ,  H05K2201/09672 ,  H05K2201/10151

Abstract: A printed circuit board (P) has an evaluation device (E) and an electrode configuration of a capacitive sensor, wherein the electrode configuration has at least two electrodes, one arranged above the other and spaced apart from each other, which each are formed by portions of at least one electrically conductive layer of the printed circuit board (P), and wherein at least one electrode of the electrode configuration is coupled with the evaluation device (E) via a conductor path of the printed circuit board (P). Furthermore, an electric handheld device may have at least one such printed circuit board (P).

Abstract translation: 印刷电路板（P）具有评价装置（E）和电容式传感器的电极结构，其中电极结构具有至少两个电极，一个彼此并排设置并彼此间隔开，每个电极由 印刷电路板（P）的至少一个导电层的部分，并且其中电极结构的至少一个电极经由印刷电路板（P）的导体路径与评估装置（E）耦合。 此外，电动手持装置可以具有至少一个这样的印刷电路板（P）。

公开(公告)号：US20140133107A1

公开(公告)日：2014-05-15

申请号：US14078033

申请日：2013-11-12

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Geon Se CHANG ,  Sung Kwon WI ,  Yong Suk KIM

IPC: H05K1/16

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H05K3/0052 ,  H05K2201/09672 ,  H05K2203/061 ,  Y10T29/4902

Abstract: Disclosed herein is a thin film type chip device, including: a plurality of unit circuit structures laminated on a substrate; and an adhesive layer adhering the unit circuit structures to each other.

Abstract translation: 本文公开了一种薄膜型芯片器件，包括：层叠在基板上的多个单位电路结构; 以及将单元电路结构彼此粘合的粘合剂层。

公开(公告)号：US20140036467A1

公开(公告)日：2014-02-06

申请号：US13751358

申请日：2013-01-28

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yoshihito OTSUBO

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H05K3/00 ,  H05K3/4629 ,  H05K2201/0187 ,  H05K2201/09136 ,  H05K2201/09672

Abstract: A ceramic multilayer substrate includes stacked ceramic layers; internal conductors which are stacked with one of the ceramic layers therebetween, and are arranged such that at least a portion of the internal conductors overlap each other in a stacking direction; and a constraining layer which is arranged on a layer different from layers on which the internal conductors are located. The constraining layer overlaps, in the stacking direction, an internal conductor-overlapping region where at least two of the internal conductors overlapping each other in the stacking direction, has a planar area not more than twice the planar area of the internal conductor-overlapping region, and contains an unsintered inorganic material powder. The constraining layer has a planar area not more than one-half the planar area of the ceramic layers. The constraining layer is arranged so as to entirely cover the internal conductor-overlapping region.

Abstract translation: 陶瓷多层基板包括层叠的陶瓷层; 内部导体，其间层叠有陶瓷层之一，并且布置成使得内部导体的至少一部分在堆叠方向上彼此重叠; 以及布置在与内部导体所在的层不同的层上的约束层。 约束层在堆叠方向上重叠内部导体重叠区域，其中至少两个内部导体在层叠方向上彼此重叠，具有不大于内部导体重叠区域的平面面积的两倍的平面面积 ，并含有未烧结的无机材料粉末。 约束层具有不超过陶瓷层的平面面积的一半的平面面积。 约束层被布置成完全覆盖内部导体重叠区域。

公开(公告)号：US20140034376A1

公开(公告)日：2014-02-06

申请号：US13957017

申请日：2013-08-01

Applicant: Samtec, Inc.

Inventor： Gary Ellsworth BIDDLE

IPC: H05K1/02

CPC classification number: H01P3/081 ,  H01P3/026 ,  H01P5/028 ,  H01P5/08 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/115 ,  H05K1/118 ,  H05K1/14 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2201/0979

Abstract: A substrate including a first transmission line arranged to transmit electrical signals and including first and second traces and a first dielectric layer. The first and second traces are separated from each other by the first dielectric layer. A printed circuit board includes a first transmission line arranged to transmit electrical signals and including first, second, and third traces; and a first dielectric layer. The first and second traces are separated from the third trace by the first dielectric layer.

Abstract translation: 一种衬底，包括布置成传输电信号并且包括第一和第二迹线的第一传输线和第一介电层。 第一和第二迹线通过第一介电层彼此分离。 印刷电路板包括布置成传输电信号并且包括第一，第二和第三迹线的第一传输线; 和第一电介质层。 第一和第二迹线通过第一介电层与第三迹线分离。

公开(公告)号：US20140034373A1

公开(公告)日：2014-02-06

申请号：US13954431

申请日：2013-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Kazuhiro YOSHIKAWA ,  Yasuhiko MANO

IPC: H01F5/00 ,  H01F41/32 ,  H05K1/16

CPC classification number: H01F5/003 ,  H01F5/00 ,  H01F17/0013 ,  H01F41/32 ,  H01F2017/0066 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/083 ,  H05K2201/09672 ,  Y10T29/4902

Abstract: An inductor element has a support layer, a first conductive layer formed on the support layer and having a first inductor pattern and a first pad at one end of the first inductor pattern, a first insulation layer formed on the support layer and first conductive layer and including a magnetic material layer and a resin layer, a second conductive layer formed on the first insulation layer and having a second inductor pattern and a second pad at one end of the second inductor pattern, and a via conductor formed through the first insulation layer and connecting the first and second conductive layers. The magnetic material layer is covering at least part of the first inductor pattern, the resin layer is covering the first pad and has opening exposing at least part of the first pad, and the via conductor is formed in the opening of the first insulation layer.

Abstract translation: 电感器元件具有支撑层，形成在支撑层上并具有第一电感器图案的第一导电层和位于第一电感器图案的一端的第一焊盘，形成在支撑层和第一导电层上的第一绝缘层和 包括磁性材料层和树脂层，形成在第一绝缘层上并具有第二电感器图案的第二导电层和在第二电感器图案的一端的第二焊盘，以及通过第一绝缘层形成的通孔导体和 连接第一和第二导电层。 磁性材料层覆盖第一电感器图案的至少一部分，树脂层覆盖第一焊盘，并且具有暴露第一焊盘的至少一部分的开口，并且通孔导体形成在第一绝缘层的开口中。