公开(公告)号：US09049786B2

公开(公告)日：2015-06-02

申请号：US13436005

申请日：2012-03-30

Applicant: Toshihisa Nomura ,  Kenji Suzuki ,  Kazushige Akita

Inventor： Toshihisa Nomura ,  Kenji Suzuki ,  Kazushige Akita

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/02 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  G01R1/073 ,  G01R3/00

CPC classification number: H05K1/0287 ,  G01R1/07342 ,  G01R3/00 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/005 ,  H05K3/4061 ,  H05K3/429 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/0979 ,  Y10T156/11

Abstract: A ceramic substrate for an electronic part inspecting apparatus that can be manufactured in accordance with predetermined specifications, regardless of the number and location of pins required, relatively quickly and inexpensively is provided. In certain embodiments the ceramic substrate is configured to connect to a probe for inspecting an electronic component, and the ceramic substrate comprises a plurality of vias located in a center area of the ceramic substrate that penetrate through the ceramic substrate in its thicknesswise direction, pads located in an outer periphery that surrounds the center area where the vias are located, the pads being configured to connected to the probes, and a conductive layer located only over the front surface of the ceramic substrate and connects the vias to the respective pads. Certain embodiments comprise a greater number of vias than pins. A method of manufacturing the ceramic substrate is also provided.

Abstract translation: 提供了一种用于电子部件检查装置的陶瓷基板，其可以根据预定规格制造，而不管所需的销的数量和位置如何，相对快速且低成本地进行。 在某些实施例中，陶瓷衬底被配置为连接到用于检查电子部件的探针，并且陶瓷衬底包括位于陶瓷衬底的沿其厚度方向穿过陶瓷衬底的中心区域的多个通孔，位于 在围绕通孔所在的中心区域的外周中，衬垫被配置为连接到探针，以及导电层，其仅位于陶瓷衬底的前表面上，并将通孔连接到相应的焊盘。 某些实施例包括比引脚更多的通孔。 还提供了制造陶瓷基板的方法。

公开(公告)号：US09030021B2

公开(公告)日：2015-05-12

申请号：US13227986

申请日：2011-09-08

Applicant: Jik-ho Song

Inventor： Jik-ho Song

IPC: H01L23/498 ,  H05K1/11 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

CPC classification number: H05K1/113 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0979 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147

Abstract: Provided are a printed circuit board (PCB) having hexagonally aligned bump pads as a substrate of a semiconductor package, and a semiconductor package including the same. The PCB includes: a PCB body; a bottom metal layer at a bottom of the PCB body; and a top metal layer at a top of the PCB body, and the top metal layer includes: vias vertically connected to the PCB body; bump pads hexagonally aligned in a horizontal direction around the vias; and connection patterns connecting the vias to two or more of the bump pads. Accordingly, the number of bump pads in a unit area of the PCB may be increased.

Abstract translation: 提供了具有六边形对准的凸块焊盘作为半导体封装的衬底的印刷电路板（PCB）和包括该半导体封装的半导体封装。 PCB包括：PCB体; PCB底部的底部金属层; 以及位于PCB主体顶部的顶部金属层，顶部金属层包括：垂直连接到PCB主体的通孔; 突起焊盘在通孔周围沿水平方向六边形排列; 以及将通孔连接到两个或更多个凸块的连接图案。 因此，可以增加PCB的单位面积中的凸块的数量。

公开(公告)号：US09018832B2

公开(公告)日：2015-04-28

申请号：US13242329

申请日：2011-09-23

Applicant: Makoto Agatani ,  Toshio Hata ,  Tomokazu Nada ,  Shinya Ishizaki

Inventor： Makoto Agatani ,  Toshio Hata ,  Tomokazu Nada ,  Shinya Ishizaki

IPC: H01L33/62 ,  H01L27/00 ,  F21V23/06 ,  F21K99/00 ,  H05K1/11 ,  H01L25/075 ,  H01L33/52

CPC classification number: H01L25/0753 ,  F21K9/00 ,  F21K9/232 ,  F21V23/06 ,  F21Y2101/00 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L33/483 ,  H01L33/52 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/01327 ,  H01L2933/0066 ,  H05K1/11 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2201/0979 ,  H05K2201/10106 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical use, by both connecting methods with a solder and a connector, and a lighting device provided with the light-emitting device are provided. The light-emitting device according to the present invention has a plurality of LED chips, and a soldering electrode land and a connector connecting electrode land electrically connected to the chips, on a ceramic substrate. The soldering electrode land is formed of a first conductive material having a function to prevent diffusion to a solder, and the connector connecting electrode land is formed of a second conductive material having a function to prevent oxidation.

Abstract translation: 一种能够确保发光元件和电极之间的电连接而不会在实际使用中产生任何问题的发光装置，通过两种连接方法与焊料和连接器，以及设置有发光装置的照明装置 被提供。 根据本发明的发光装置在陶瓷基板上具有多个LED芯片，以及焊接电极焊盘和与芯片电连接的连接器连接电极焊盘。 焊接电极焊盘由具有防止向焊料扩散的功能的第一导电材料形成，并且连接器连接电极焊盘由具有防止氧化功能的第二导电材料形成。

公开(公告)号：US20150091675A1

公开(公告)日：2015-04-02

申请号：US14568341

申请日：2014-12-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO

IPC: H01P3/08

CPC classification number: H01P3/082 ,  H01P1/20363 ,  H01P3/084 ,  H01P3/085 ,  H05K1/0225 ,  H05K1/0242 ,  H05K1/115 ,  H05K1/147 ,  H05K2201/09618 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: A high-frequency signal line includes a dielectric body including a first dielectric layer and one or more other dielectric layers laminated together. A first signal line is provided on a first main surface, which is a main surface located on one side in a direction of lamination, of the first dielectric layer. A second signal line is provided on a second main surface, which is a main surface located on another side in the lamination direction, of the first dielectric layer so as to face the first signal line via the first dielectric layer. The second signal line is electrically connected to the first signal line. A first ground conductor is located on one side in the lamination direction than the first signal line. A second ground conductor is located on another side in the lamination direction than the second signal line.

Abstract translation: 高频信号线包括电介体，其包括第一电介质层和层叠在一起的一个或多个其它电介质层。 第一信号线设置在第一介电层的位于层叠方向一侧的主表面的第一主表面上。 第二信号线被设置在第一介电层的位于层叠方向另一侧的主表面的第二主表面上，以便经由第一介电层面对第一信号线。 第二信号线电连接到第一信号线。 第一接地导体位于比第一信号线在层叠方向的一侧。 第二接地导体位于层叠方向上的另一侧，而不是第二信号线。

公开(公告)号：US20150060395A1

公开(公告)日：2015-03-05

申请号：US14012240

申请日：2013-08-28

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: H05K3/12

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing a first stamp and a multi-level second stamp. A curable bottom layer and multi-layer are provided on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer. A multi-layer micro-channel and a top-layer micro-channel are imprinted in the multi-layer. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire extends from the central area into the edge area. The multi-layer micro-wire contacts the bottom-layer micro-wire in the edge area. The top-layer micro-wire is over the central area and is separate from the multi-layer micro-wire and the bottom-layer micro-channel. The bottom-layer micro-wire is electrically connected to the multi-layer micro-wire and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一印模和多级第二印模。 在基板上设置有可固化的底层和多层。 底层微通道印在底层中。 多层微通道和顶层微通道印在多层中。 微线形成在每个微通道中。 底层微线从中心区域延伸到边缘区域。 多层微线接触边缘区域的底层微线。 顶层微线在中心区域之上，与多层微线和底层微通道分离。 底层微线电连接到多层微线，并与顶层微线电隔离。

公开(公告)号：US20150060394A1

公开(公告)日：2015-03-05

申请号：US14012216

申请日：2013-08-28

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: H05K3/12

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing first, second, and third different stamps. A curable bottom, connecting layer, and top layer are formed on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer in the central area and the edge area, a connecting-layer micro-channel is imprinted in the connecting layer in the edge area over the bottom-layer micro-channel, an edge micro-channel is imprinted in the top layer in the edge area over the connecting-layer micro-channel, and top-layer micro-channels are imprinted in the top layer over the central area. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一，第二和第三不同的邮票。 在基板上形成可固化的底部，连接层和顶层。 底层微通道印在中心区域和边缘区域的底层中，连接层微通道被压印在底层微通道上的边缘区域中的连接层中，边缘 微通道印在连接层微通道上的边缘区域的顶层中，顶层微通道印在中心区域的顶层中。 微线形成在每个微通道中。 中心区域的底层微线电连接到边缘区域中的边缘微线，并与顶层微线电隔离。

公开(公告)号：US20150016066A1

公开(公告)日：2015-01-15

申请号：US14192559

申请日：2014-02-27

Applicant: Taiyo Yuden Co., Ltd.

Inventor： Masaya SHIMAMURA ,  Eiji MUGIYA ,  Kenzo KITAZAKI ,  Takehiko KAI ,  Masafumi Imai ,  Atsushi ITO

IPC: H05K9/00 ,  H05K3/28 ,  H05K5/06 ,  H05K3/22

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H05K1/0215 ,  H05K1/0216 ,  H05K3/284 ,  H05K2201/0919 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0191 ,  H05K2203/085 ,  H05K2203/1316 ,  Y10T29/49146 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A circuit module includes a wiring substrate, an electronic component, a sealing layer, and a conductive shield. The wiring substrate has a mount surface. The electronic component is mounted on the mount surface. The sealing layer is formed of an insulating material, covers the electronic component, and has a first surface and a second surface, the first surface being opposite to the mount surface and having a first sealing area and a second sealing area, the second sealing area projecting from the first sealing area to an opposite side of the mount surface, the second surface being connected to the mount surface and the first surface. The conductive shield covers at least the second surface and the first sealing area of the first surface.

Abstract translation: 电路模块包括布线基板，电子部件，密封层和导电屏蔽。 布线基板具有安装面。 电子部件安装在安装面上。 密封层由绝缘材料形成，覆盖电子部件，并且具有第一表面和第二表面，第一表面与安装表面相对并具有第一密封区域和第二密封区域，第二密封区域 从第一密封区域突出到安装表面的相对侧，第二表面连接到安装表面和第一表面。 导电屏蔽至少覆盖第一表面的第二表面和第一密封区域。

公开(公告)号：US20140332252A1

公开(公告)日：2014-11-13

申请号：US13965194

申请日：2013-08-13

Applicant: Unimicron Technology Corp.

Inventor： Chun-Ting Lin

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/40 ,  H01L21/67265 ,  H01L21/673 ,  H01L21/67346 ,  H01L21/67763 ,  H01L21/6779 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H05K1/11 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0979 ,  H05K2203/0369 ,  H05K2203/0376 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00

Abstract: A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.

Abstract translation: 载体基板包括绝缘层，导电塔和电路结构层。 每个导电塔的直径从顶表面逐渐增加到底表面，并且导电塔包括第一导电塔和围绕第一导电塔的第二导电塔。 电路结构层设置在绝缘层上，并且包括至少一个电介质层，至少两个电路层和第一导电通孔。 每个第二导电塔对应地连接到第一导电通孔中的至少两个，并且每个第一导电塔对应地连接到第一导电通孔之一。 在第一导电通孔和第一和第二导电塔之间存在界面。

公开(公告)号：US20140268783A1

公开(公告)日：2014-09-18

申请号：US14243521

申请日：2014-04-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Makoto AGATANI ,  Toshio HATA ,  Tomokazu NADA ,  Shinya ISHIZAKI

IPC: F21V23/06 ,  F21K99/00

CPC classification number: H01L25/0753 ,  F21K9/00 ,  F21K9/232 ,  F21V23/06 ,  F21Y2101/00 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L33/483 ,  H01L33/52 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/01327 ,  H01L2933/0066 ,  H05K1/11 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2201/0979 ,  H05K2201/10106 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical use, by both connecting methods with a solder and a connector, and a lighting device provided with the light-emitting device are provided. The light-emitting device according to the present invention has a plurality of LED chips, and a soldering electrode land and a connector connecting electrode land electrically connected to the chips, on a ceramic substrate. The soldering electrode land is formed of a first conductive material having a function to prevent diffusion to a solder, and the connector connecting electrode land is formed of a second conductive material having a function to prevent oxidation.

Abstract translation: 一种能够确保发光元件和电极之间的电连接而不会在实际使用中产生任何问题的发光装置，通过两种连接方法与焊料和连接器，以及设置有发光装置的照明装置 被提供。 根据本发明的发光装置在陶瓷基板上具有多个LED芯片，以及焊接电极焊盘和与芯片电连接的连接器连接电极焊盘。 焊接电极焊盘由具有防止向焊料扩散的功能的第一导电材料形成，并且连接器连接电极焊盘由具有防止氧化功能的第二导电材料形成。

公开(公告)号：US08819933B2

公开(公告)日：2014-09-02

申请号：US12957431

申请日：2010-12-01

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H01R43/02

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49179 ,  H01L2924/00

Abstract: A method for forming an electrical structure. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract translation: 一种形成电结构的方法。 电结构包括互连结构和衬底。 衬底包括导电焊盘和电连接到导电焊盘的多个导线迹线。 导电焊盘电连接和机械连接到互连结构。 多条导线包括第一线迹线，第二线迹线，第三线迹线和第四线迹线。 第一线迹和第二线迹均电连接到导电垫的第一侧。 第三线迹电连接到导电垫的第二侧。 第四线迹电连接到所述第一导电焊盘的第三侧。 多个导线配置成分布电流。