公开(公告)号：US08294041B2

公开(公告)日：2012-10-23

申请号：US12170082

申请日：2008-07-09

Applicant: Cheng-Po Yu ,  Cheng-Hung Yu

Inventor： Cheng-Po Yu ,  Cheng-Hung Yu

IPC: H05K1/11

CPC classification number: H05K1/0231 ,  H05K1/0219 ,  H05K1/162 ,  H05K3/107 ,  H05K2201/09036 ,  H05K2201/09809 ,  Y10T29/49117

Abstract: A circuit board including a first dielectric layer having a first surface and a second surface, a first circuit layer, a second dielectric layer, and a second circuit layer is provided. At least one trench is formed on the first surface, and the first circuit layer is formed on an inside wall of the trench. In addition, the second dielectric layer is disposed in the trench, and covers the first circuit layer. The second circuit layer is disposed in the trench, and the second dielectric layer is located between the first circuit layer and the second circuit layer. A manufacturing method of the circuit board is further provided.

Abstract translation: 提供一种电路板，包括具有第一表面和第二表面的第一介电层，第一电路层，第二电介质层和第二电路层。 在第一表面上形成至少一个沟槽，并且第一电路层形成在沟槽的内壁上。 此外，第二电介质层设置在沟槽中并覆盖第一电路层。 第二电路层设置在沟槽中，第二电介质层位于第一电路层和第二电路层之间。 还提供了电路板的制造方法。

公开(公告)号：US08247883B2

公开(公告)日：2012-08-21

申请号：US12328694

申请日：2008-12-04

Applicant: Jurgen H. Daniel ,  Tse Nga Ng

Inventor： Jurgen H. Daniel ,  Tse Nga Ng

IPC: H01L23/522

CPC classification number: H05K1/0221 ,  H01L2924/0002 ,  H05K1/056 ,  H05K3/12 ,  H05K2201/09809 ,  H05K2201/09981 ,  H01L2924/00

Abstract: An embodiment is a method and apparatus to construct a shielded cable, wire, or circuit. A first insulator layer is deposited on a first conductor or semiconductor layer. A second conductor or semiconductor layer is deposited on the first insulator layer. A second insulator layer is deposited on the first insulator layer. The second insulator layer covers the second conductor or semiconductor layer and defines a shielded region. A third conductor or semiconductor layer is deposited on the first conductor or semiconductor layer. The third conductor or semiconductor layer covers the first and second insulator layers. At least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing.

Abstract translation: 实施例是构造屏蔽电缆，导线或电路的方法和装置。 第一绝缘体层沉积在第一导体或半导体层上。 第二导体或半导体层沉积在第一绝缘体层上。 第二绝缘体层沉积在第一绝缘体层上。 第二绝缘体层覆盖第二导体或半导体层并且限定屏蔽区域。 第三导体或半导体层沉积在第一导体或半导体层上。 第三导体或半导体层覆盖第一和第二绝缘体层。 第一，第二和第三导体或半导体层中的至少一个以及通过印刷沉积第一和第二绝缘体层。

公开(公告)号：US08148647B2

公开(公告)日：2012-04-03

申请号：US11832376

申请日：2007-08-01

Applicant: Souhei Samejima ,  Sadao Sato ,  Hiroyuki Osuga ,  Shigeru Utsumi ,  Teruhiko Kumada

Inventor： Souhei Samejima ,  Sadao Sato ,  Hiroyuki Osuga ,  Shigeru Utsumi ,  Teruhiko Kumada

IPC: H05K1/11

CPC classification number: H05K3/4641 ,  H05K1/056 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0281 ,  H05K2201/0323 ,  H05K2201/09809 ,  Y10T29/49155

Abstract: An object of the invention is to provide a printed circuit board that has an excellent heat dissipation performance and excellent reliability, and its manufacturing method. The printed circuit board includes: prepregs (2a) and (2b) being cured after each covering the surfaces of a metal plate (1) provided with first throughholes (1a) therein and the inner walls of the first throughholes (1a); prepregs (4a) and (4b) being cured after glass clothes (3a) and (3b) are sandwiched between the prepregs (2a) and (2b), and the prepregs (4a) and (4b), respectively; and second throughholes (8) that connect wiring layers (7a) and (7c), and (7b) and (7d) provided on both surfaces of prepregs (6a) and (6b), respectively. The prepregs (2a) and (2b) and the prepregs (4a) and (4b) are characterized in that they contain inorganic filler. Furthermore, the prepregs (2a) and (2b) and the prepregs (4a) and (4b) may contain elastomer.

Abstract translation: 本发明的目的是提供一种具有优异的散热性能和优异的可靠性的印刷电路板及其制造方法。 印刷电路板包括：在每个覆盖设置有第一通孔（1a）的金属板（1）的表面和第一通孔（1a）的内壁之后，预浸料（2a）和（2b）固化; 玻璃衣服（3a）和（3b）夹在预浸料（2a）和（2b）之间，以及预浸料坯（4a）和（4b）分别固化的预浸料坯（4a）和（4b） 以及分别设置在预浸料坯（6a）和（6b）的两个表面上的布线层（7a）和（7c）和（7b）和（7d）的第二通孔（8）。 预浸料（2a）和（2b）和预浸料（4a）和（4b）的特征在于它们含有无机填料。 此外，预浸料（2a）和（2b）和预浸料（4a）和（4b）可以含有弹性体。

公开(公告)号：US08143976B2

公开(公告)日：2012-03-27

申请号：US12607027

申请日：2009-10-27

Applicant: Christopher P. Wyland

Inventor： Christopher P. Wyland

IPC: H01P7/08 ,  H03H7/38

CPC classification number: H01L23/66 ,  H01L23/64 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09463 ,  H05K2201/09781 ,  H05K2201/09809 ,  H01L2924/00

Abstract: Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments of the present invention avoid impedance mismatch in circuits and achieve an advance in the art by providing a via with higher impedance through the addition of split ring resonators (SSRs) to each end of the via.

Abstract translation: 差分信号的通孔通常比与其相连的信号线阻抗更低。 导致阻抗失配的噪声和反射信号可能要求电路以远低于所需的频率运行。 本发明的一个或多个实施例避免了电路中的阻抗不匹配，并且通过向通孔的每个端部添加裂环谐振器（SSR）提供具有较高阻抗的通孔来实现本领域的进步。

公开(公告)号：US20120045909A1

公开(公告)日：2012-02-23

申请号：US13264892

申请日：2010-03-26

Applicant: Erich Pischler

Inventor： Erich Pischler

IPC: H01R12/71 ,  H01R43/00

CPC classification number: H01L24/10 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/72 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2223/6622 ,  H01L2224/0401 ,  H01L2224/05578 ,  H01L2224/13 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/16106 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81898 ,  H01L2224/83136 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01R23/26 ,  H01R24/40 ,  H01R2103/00 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/184 ,  H05K2201/09036 ,  H05K2201/092 ,  H05K2201/09809 ,  H05K2201/09845 ,  Y10T29/49117 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A male connection component (120) for connection with a correspondingly configured female connection component (140) having a recess (144) extending into a main surface (170) of a female Substrate (142) of the female connection component (140), wherein the female connection component (140) comprises a plurality of electrically conductive female contacts (146) which are electrically decoupled from one another and are arranged at different height levels with regard to the main surface (170) of the female Substrate (142), the male connection component (120) comprising a male Substrate (102), a Protrusion (104) protruding from a main surface (160) of the male Substrate (102) and comprising a plurality of electrically conductive male contacts (106) which are electrically decoupled from one another and are arranged at different height levels with regard to the main surface (160) of the male Substrate (102), wherein the male connection component (120) is adapted for connection with the female connection component (140) so that upon connection, each of the plurality of electrically conductive male contacts (106) is brought in contact with one of the plurality of electrically conductive female contacts (146) for providing electric contactation at different height levels, wherein the male Substrate (102) forms at least part of one of a chip, a chip package and a circuit board.

Abstract translation: 用于与相应配置的阴连接部件（140）连接的阳连接部件（120），该阴连接部件具有延伸到阴连接部件（140）的阴基板（142）的主表面（170）的凹部（144），其中 阴连接部件（140）包括多个导电阴触头（146），它们彼此电分离并且相对于阴基板（142）的主表面（170）布置在不同的高度水平处， 阳连接部件（120），包括阳基底（102），从阳基底（102）的主表面（160）突出的突起（104），并且包括多个导电的阳触头（106），电接头 并且相对于阳性基板（102）的主表面（160）布置在不同的高度水平处，其中阳连接部件（120）适于与阴连接 连接部件（140），使得在连接时，多个导电阳触头（106）中的每一个与多个导电阴触头（146）中的一个接触，用于在不同的高度级别提供电接触，​​其中 阳基板（102）形成芯片，芯片封装和电路板之一的至少一部分。

公开(公告)号：US20120019267A1

公开(公告)日：2012-01-26

申请号：US13185060

申请日：2011-07-18

Applicant: Isao TABUCHI

Inventor： Isao TABUCHI

IPC: G01R27/26

CPC classification number: G01R15/18 ,  H01B11/00 ,  H01F5/003 ,  H01F27/2804 ,  H01L27/00 ,  H01Q1/00 ,  H01Q1/38 ,  H01Q7/00 ,  H01R9/00 ,  H05H1/0081 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10015 ,  H05K2201/10151

Abstract: The present invention provides a high frequency detection device that detects a high frequency voltage signal according to a high frequency voltage generated in a power transmission body. The high frequency detection device includes a substrate and a capacitance conductor fixed to the substrate. The capacitance conductor includes a penetration portion and a capacitor electrode. In the penetration portion, the power transmission body is disposed so as to extend along the penetration portion in a state in which the axial direction of the power transmission body and the substrate are substantially orthogonal. The capacitor electrode is provided to be opposed to the power transmission body.

Abstract translation: 本发明提供一种高频检测装置，其根据在动力传递体中产生的高频电压来检测高频电压信号。 高频检测装置包括固定到基板的基板和电容导体。 电容导体包括穿透部分和电容器电极。 在穿透部中，动力传递体在动力传递体和基底的轴向大致正交的状态下配置成沿着贯通部延伸。 电容器电极设置成与电力传输体相对。

公开(公告)号：US08084695B2

公开(公告)日：2011-12-27

申请号：US11651338

申请日：2007-01-10

Applicant: Hsiuan-ju Hsu ,  Richard Walter Ziolkowski

Inventor： Hsiuan-ju Hsu ,  Richard Walter Ziolkowski

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/115 ,  H01L2924/0002 ,  H05K1/0222 ,  H05K1/0251 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0715 ,  H05K2201/09809 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The embodiment of the invention is about a novel via structure which can be incorporated into printed circuit boards, integrated circuit packages, and integrated circuits in order to reduce crosstalk, to improve signal integrity and to achieve EM emission compliance. A 4-layer (2 signal layers and 2 power layers or 2 signal layers and 2 ground layers) circuit board assembly was used for demonstrating the effect of the novel via structure. The same concept can be applied to any multi-layer circuit board. Layers that have an electrical property can be added above, under, or within the basic 4-layer circuit board to achieve a multi-layer circuit board. For 2-layer and 3-layer circuit boards, a deformed version of the proposed via structure based upon the same concept will be needed for a coplanar waveguide configuration.

Abstract translation: 本发明的实施例涉及一种新颖的通孔结构，其可并入印刷电路板，集成电路封装和集成电路中，以便减少串扰，提高信号完整性并实现EM发射顺应性。 使用4层（2个信号层和2个功率层或2个信号层和2个接地层）电路板组件来证明新型通孔结构的效果。 相同的概念可以应用于任何多层电路板。 具有电性能的层可以添加到基本4层电路板的上方，下面或内部，以实现多层电路板。 对于2层和3层电路板，对于共面波导配置，将需要基于相同概念的所提出的通孔结构的变形形式。

公开(公告)号：US08079667B2

公开(公告)日：2011-12-20

申请号：US12338169

申请日：2008-12-18

Applicant: Michael Y. Young ,  Patrick C. Cheung ,  Stephen David White ,  John R. Andrews ,  David J. Gervasi

Inventor： Michael Y. Young ,  Patrick C. Cheung ,  Stephen David White ,  John R. Andrews ,  David J. Gervasi

IPC: B41J2/14 ,  B41J2/05 ,  B41J2/045

CPC classification number: B41J2/14233 ,  B41J2002/14306 ,  B41J2002/14491 ,  B41J2202/18 ,  H05K1/0272 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09581 ,  H05K2201/09809 ,  H05K2203/0315

Abstract: A drop generator having a via structure configured for electrical and fluidic interconnection. The via structure includes an electrically conductive layer and an electrically insulating layer disposed on the electrically conductive layer.

Abstract translation: 具有经配置以用于电和流体互连的通孔结构的液滴发生器。 通孔结构包括导电层和设置在导电层上的电绝缘层。

公开(公告)号：US20110296678A1

公开(公告)日：2011-12-08

申请号：US13134259

申请日：2011-06-02

Applicant: James Russell

Inventor： James Russell

IPC: H05K3/00 ,  B23P19/00

CPC classification number: H05K3/32 ,  H05K1/0222 ,  H05K3/325 ,  H05K3/34 ,  H05K3/429 ,  H05K2201/09481 ,  H05K2201/09809 ,  H05K2201/10356 ,  Y10T29/49124 ,  Y10T29/532

Abstract: A method and an apparatus for connecting a coaxial (or a micro coaxial) cable to the bottom side of a printed circuit board (PCB) in order to improve signal integrity of a test circuit. A coaxial or a micro coaxial cable is directly connected to a coaxial cable to the bottom sides of pads located on an exterior later of the PCB.

Abstract translation: 一种用于将同轴（或微同轴）电缆连接到印刷电路板（PCB）的底侧的方法和装置，以便提高测试电路的信号完整性。 同轴或微同轴电缆直接连接到位于PCB后面的焊盘的底侧的同轴电缆。

公开(公告)号：US20110290408A1

公开(公告)日：2011-12-01

申请号：US13142113

申请日：2009-12-24

Applicant: Sohei Samejima ,  Tsuyoshi Ozaki ,  Hiroyuki Osuga ,  Teruhiko Kumada

Inventor： Sohei Samejima ,  Tsuyoshi Ozaki ,  Hiroyuki Osuga ,  Teruhiko Kumada

IPC: H05K3/46

CPC classification number: H05K3/445 ,  H05K3/0011 ,  H05K3/40 ,  H05K3/429 ,  H05K3/462 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0323 ,  H05K2201/0347 ,  H05K2201/09809

Abstract: A method of manufacturing a printed wiring board (10) includes the steps of: forming a core including carbon fiber reinforced plastic having a primary through hole (3a); forming a first adhesive member (4a) on a lower surface of the core to cover the primary through hole (3a); charging an insulating member into the primary through hole (3a); forming a second adhesive member (4b) on an upper surface of the core; forming a third adhesive member (6a) below the first adhesive member (4a); forming a fourth adhesive member (6b) on the second adhesive member (4b); and forming interconnections on the core.

Abstract translation: 制造印刷电路板（10）的方法包括以下步骤：形成包括具有主通孔（3a）的碳纤维增强塑料的芯体; 在所述芯的下表面上形成第一粘合构件（4a）以覆盖所述主通孔（3a）; 将绝缘构件加载到所述主通孔（3a）中; 在所述芯的上表面上形成第二粘合构件（4b）; 在所述第一粘合部件（4a）的下方形成第三粘接部件（6a）。 在第二粘合部件（4b）上形成第四粘合部件（6b）; 并在芯上形成互连。