公开(公告)号：US20090139758A1

公开(公告)日：2009-06-04

申请号：US12155401

申请日：2008-06-03

Applicant: Hyo Young Shin ,  Seung Boo Jung ,  Young Jun Moon ,  Soon Min Hong ,  Chang Yong Lee ,  Ja Myeong Koo ,  Hyun Tae Kim ,  Jong Bum Lee ,  Hyun Joo Han

Inventor： Hyo Young Shin ,  Seung Boo Jung ,  Young Jun Moon ,  Soon Min Hong ,  Chang Yong Lee ,  Ja Myeong Koo ,  Hyun Tae Kim ,  Jong Bum Lee ,  Hyun Joo Han

IPC: H05K3/36 ,  H01R12/04

CPC classification number: H05K3/361 ,  H05K3/328 ,  H05K3/3452 ,  H05K3/363 ,  H05K2201/09881 ,  H05K2201/0989 ,  H05K2203/0285 ,  H05K2203/167 ,  Y10T29/49126

Abstract: A printed circuit board (PCB) assembly is disclosed, which includes a first PCB on which a plurality of first electrode terminals are arranged at intervals from one another; a second PCB on which a plurality of second electrode terminals respectively connected with the first electrode terminals are arranged at intervals from one another; and separation preventing member which prevents the first and the second electrode terminals from deviating from their correct positions when the first and the second electrode terminals are ultrasonically-welded to each other. Accordingly, lateral movement of the first and the second PCBs relative to each other is restricted owing to the separation preventing member, the plurality of first electrode terminals and second electrode terminals can be bonded to each other without deviating from their correct positions.

Abstract translation: 公开了一种印刷电路板（PCB）组件，其包括第一PCB，多个第一电极端子彼此间隔布置在该第一PCB上; 分别与第一电极端子分别连接的多个第二电极端子彼此间隔布置的第二PCB; 以及防止第一和第二电极端子在第一和第二电极端子彼此超声波焊接时偏离其正确位置的防分离部件。 因此，由于分离防止部件，第一和第二PCB的相对于彼此的横向运动受到限制，所以多个第一电极端子和第二电极端子可以彼此接合而不偏离其正确的位置。

公开(公告)号：US07538031B2

公开(公告)日：2009-05-26

申请号：US11235645

申请日：2005-09-26

Applicant: Noboru Uehara ,  Tsuyoshi Shintate ,  Kazuaki Sakurada

Inventor： Noboru Uehara ,  Tsuyoshi Shintate ,  Kazuaki Sakurada

IPC: H01L21/44

CPC classification number: H05K3/125 ,  H05K3/4647 ,  H05K3/4664 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/1173 ,  Y10T29/49162

Abstract: A method of manufacturing a wiring substrate having a wiring layer formation step that includes: a first surface processing step in which surface processing is performed on a film formation area of a substrate; a wiring formation step in which a wiring pattern is formed by placing a first liquid material on the film formation area; a second surface processing step in which surface processing is once again performed on the film formation area; and an insulating film formation step in which an insulating film is formed by placing a second liquid material in gaps in the wiring pattern, wherein an affinity between the second liquid material and the film formation area in the insulating film formation step is greater than an affinity between the first liquid material and the film formation area in the wiring formation step.

Abstract translation: 一种具有布线层形成工序的布线基板的制造方法，其特征在于，包括：对基板的成膜区域进行表面处理的第一表面处理工序; 布线形成步骤，其中通过将第一液体材料放置在成膜区域上而形成布线图案; 第二表面处理步骤，其中再次对成膜区域进行表面处理; 以及绝缘膜形成步骤，其中通过将第二液体材料放置在布线图案的间隙中而形成绝缘膜，其中第二液体材料与绝缘膜形成步骤中的成膜区域之间的亲合力大于亲和力 在布线形成步骤中在第一液体材料和成膜区域之间。

公开(公告)号：US20090119915A1

公开(公告)日：2009-05-14

申请号：US12352372

申请日：2009-01-12

Applicant: Ryosuke Usui ,  Hideki Mizuhara ,  Yusuke Igarashi ,  Nobuhisa Takakusaki ,  Hayato Aba ,  Takeshi Nakamura

Inventor： Ryosuke Usui ,  Hideki Mizuhara ,  Yusuke Igarashi ,  Nobuhisa Takakusaki ,  Hayato Aba ,  Takeshi Nakamura

IPC: H05K3/00 ,  H05K3/02 ,  H05K3/40 ,  H05K3/42

CPC classification number: H01L21/486 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L24/73 ,  H01L24/97 ,  H01L25/16 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/0035 ,  H05K3/284 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4647 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.

Abstract translation: 本发明提供一种适于通过绝缘层将多层叠布线层彼此连接的电路装置的制造方法。 在本发明的混合集成电路器件的制造方法中，通过在第一绝缘层上层叠第一导电膜，对第一导电膜进行构图来形成第一绞合层。 在第一布线层中，形成沿厚度方向突出的第一连接部。 此外，包括第一连接部的第一布线层被第二绝缘层覆盖。 第二绝缘层由第一树脂膜和第二树脂膜形成。 第二树脂膜比第一树脂膜含有更少的无机填料。 因此，具有可以容易地形成通孔的优点。

公开(公告)号：US07529440B2

公开(公告)日：2009-05-05

申请号：US11965313

申请日：2007-12-27

Applicant: Michael W Schellinger ,  Rachid M Alameh ,  Thomas J. Pack ,  Louis J. Vannatta

Inventor： Michael W Schellinger ,  Rachid M Alameh ,  Thomas J. Pack ,  Louis J. Vannatta

IPC: G02B6/12

CPC classification number: H05K1/0274 ,  H05K2201/09236 ,  H05K2201/09881

Abstract: A circuit substrate, which supports optically and electrically conveyed signals, and method for forming the same are provided. The circuit substrate includes a substrate upon which one or more electrically conductive traces are formed, where the electrically conductive traces have areas of isolation between adjacent ones of the electrically conductive traces. The circuit substrate further includes one or more optical waveguides, where the one or more optical waveguides are in the same plane as the one or more electrically conductive traces. The optical waveguides are formed using an optically transmissive material, which is deposited in the areas of isolation between the electrical traces.

Abstract translation: 提供支持光学和电输送信号的电路基板及其形成方法。 电路衬底包括其上形成有一个或多个导电迹线的衬底，其中导电迹线在相邻的导电迹线之间具有隔离区域。 电路基板还包括一个或多个光波导，其中一个或多个光波导处于与一个或多个导电迹线相同的平面中。 使用光学透射材料形成光波导，该材料沉积在电迹线之间的隔离区域中。

公开(公告)号：US20080301934A1

公开(公告)日：2008-12-11

申请号：US12190551

申请日：2008-08-12

Applicant: George Dudnikov, JR.

Inventor： George Dudnikov, JR.

IPC: H05K3/20

CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

公开(公告)号：US20080265391A1

公开(公告)日：2008-10-30

申请号：US12169542

申请日：2008-07-08

Applicant: Terry L. STERRETT ,  Devendra NATEKAR

Inventor： Terry L. STERRETT ,  Devendra NATEKAR

IPC: H01L23/538 ,  H05K1/09

CPC classification number: H05K3/4038 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H05K3/06 ,  H05K2201/09881 ,  H05K2201/10378 ,  H05K2201/2018 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.

Abstract translation: 在一个实施例中，组装包装堆叠包括第一集成电路封装和第二集成电路封装，其使用中介层机械和电连接。 在一个实施例中，插入器106包括可以通过例如蚀刻诸如铜箔的导电构件来制造的柱状互连。 在一个应用中，柱状互连的间距或中心到中心间隔可以通过掩模技术来定义，以提供适合于特定应用的互连间距。 在另一方面，可以控制蚀刻速率以提供适合于各种应用的柱状互连的高宽比长宽比。

公开(公告)号：US20080224566A1

公开(公告)日：2008-09-18

申请号：US11684700

申请日：2007-03-12

Applicant: Vivek Bharti ,  Matthew J. Michel

Inventor： Vivek Bharti ,  Matthew J. Michel

IPC: H01L41/00 ,  B29C47/04

CPC classification number: H05K3/101 ,  B29C47/0021 ,  B29C47/062 ,  B29C47/065 ,  B29C47/145 ,  H01L21/32056 ,  H01L41/0471 ,  H01L41/083 ,  H01L41/297 ,  H01L41/333 ,  H01L41/45 ,  H05K3/4664 ,  H05K2201/09881 ,  Y10T29/42

Abstract: An article comprises first and second electrically responsive elements having a cutting plane which is perpendicular to an x-dimension for separating the elements. The conductive elements of the conductive layers are alternatingly exposed to one of the two opposing faces of the conductive element.

Abstract translation: 一种制品包括第一和第二电响应元件，其具有垂直于用于分离元件的x维度的切割平面。 导电层的导电元件交替地暴露于导电元件的两个相对面之一。

公开(公告)号：US07378326B2

公开(公告)日：2008-05-27

申请号：US11365219

申请日：2006-02-28

Applicant: Jin Yong Ahn ,  Cheol Seong Hwang ,  Sung Kun Kim ,  Chang Sup Ryu ,  Suk Hyeon Cho ,  Ho Sik Jeon

Inventor： Jin Yong Ahn ,  Cheol Seong Hwang ,  Sung Kun Kim ,  Chang Sup Ryu ,  Suk Hyeon Cho ,  Ho Sik Jeon

IPC: H01L21/20 ,  H05K3/30

CPC classification number: H05K1/162 ,  H01L2924/0002 ,  H05K1/095 ,  H05K3/108 ,  H05K3/244 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09881 ,  Y10S438/957 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.

Abstract translation: 具有嵌入式电容器的印刷电路板包括：包含形成在其外层中的第一电路层的双面覆铜层压板，所述第一电路层包括底部电极和电路图案; 通过原子层沉积在第一电路层上沉积氧化铝膜而形成的介电层; 形成在电介质层上并包括顶电极和电路图案的第二电路层; 形成在第二电路层上的单面覆铜层压板; 盲孔通孔和形成在单面覆铜层压板的预定部分中的通孔; 以及形成在盲通孔和通孔中的镀层。 还公开了印刷电路板的制造方法。

公开(公告)号：US07368998B2

公开(公告)日：2008-05-06

申请号：US11608609

申请日：2006-12-08

Applicant: Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

Inventor： Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

IPC: H03F3/14 ,  H03H7/00

CPC classification number: H05K1/0265 ,  H01L2924/1423 ,  H03F3/195 ,  H03F2200/294 ,  H05K1/165 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0542

Abstract: An inductor element containing circuit board of the present invention comprises a plurality of conductive layers, and a conductor having an inductor function (inductor conductor segment) in one or more of the conductive layers, wherein at least part of the inductor conductor segment is made thicker than other conductors disposed within the circuit board. The at least part of the inductor conductor segment extends through an insulating layer disposed between the conductive layers, or is embedded in the insulating layer, wherein the part of the inductor conductor segment has a thickness one-half or more the thickness of the insulating layer. A power amplifier module of the present invention comprises the multi-layer circuit board, a semiconductor amplifier fabricated in the multi-layer circuit board, and an impedance matching circuit coupled to the output of the semiconductor amplifier. The impedance matching circuit has a portion thereof formed of the inductor conductor segment.

Abstract translation: 本发明的电感器元件电路板包括多个导电层，以及在一个或多个导电层中具有电感器功能（电感器导体段）的导体，其中电感器导体段的至少一部分变厚 而不是设置在电路板内的其它导线。 电感器导体段的至少一部分延伸穿过设置在导电层之间的绝缘层，或者嵌入在绝缘层中，其中电感器导体段的一部分具有绝缘层的厚度的一半或更多的厚度 。 本发明的功率放大器模块包括多层电路板，在多层电路板中制造的半导体放大器和耦合到半导体放大器的输出的阻抗匹配电路。 阻抗匹配电路具有由电感器导体段形成的部分。

公开(公告)号：US20070293038A1

公开(公告)日：2007-12-20

申请号：US11890892

申请日：2007-08-08

Applicant: Hiroshi Asami ,  Hidetoshi Kusano ,  Yuji Nishitani ,  Ken Orui

Inventor： Hiroshi Asami ,  Hidetoshi Kusano ,  Yuji Nishitani ,  Ken Orui

IPC: H01L21/4763

CPC classification number: H05K3/4694 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/4617 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/09536 ,  H05K2201/09881 ,  H05K2201/09972 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.