公开(公告)号：US09183336B1

公开(公告)日：2015-11-10

申请号：US14447244

申请日：2014-07-30

Applicant: Altera Corporation

Inventor： Mark Bourgeault ,  Ryan Fung ,  David Lewis

IPC: G06F17/50 ,  H03K19/177 ,  H03K19/003

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/00323 ,  H03K19/17736

Abstract: An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals. The technique has utility for high-performance FPGAs and structured ASIC families, as well as for low-cost FPGAs and other types of logic devices.

Abstract translation: 电子设计自动化（EDA）工具改变用户的网表以提供异步信号分配的时序成功。 分配网络在分配缓冲区之前和/或之后添加流水线寄存器时使用。 或者，在异步源和目标寄存器之间插入一条流水线寄存器树。 或者，任何数量的分发网络被缝合在一起，并且可以在每个分发缓冲器之前和/或之后插入流水线阶段。 或者，通过引入偏移时钟信号的延迟分量来利用有益的偏移。 偏斜时钟信号驱动在分配缓冲器之前插入的流水线寄存器，以便提高定时裕度。 可以在EDA工具中使用各种编译技术中的任何一种来解决分配高速，高扇出异步信号的问题。 该技术可用于高性能FPGA和结构化ASIC系列，以及低成本FPGA和其他类型的逻辑器件。

公开(公告)号：US09178513B1

公开(公告)日：2015-11-03

申请号：US14135466

申请日：2013-12-19

Applicant: Altera Corporation

Inventor： Michael D. Hutton ,  David Lewis

IPC: H03K19/177 ,  H03K19/00

CPC classification number: H03K19/17776 ,  H03K19/17748 ,  H03K19/1776

Abstract: An integrated circuit may have configurable storage blocks. Multiple configurable storage blocks may share one or more internal address busses with selected configurable storage blocks having access a given address bus. An address bus may be unidirectional or bidirectional and may convey the same address signal from one configurable address block to another or to several other configurable storage blocks. Tri-state buffers or multiplexers may selectively couple or decouple the address bus between configurable storage blocks. Redundant address bus paths may bypass configurable address blocks in neighboring rows or columns allowing for disabling the respective row or column. The address bus may further have pipeline registers to allow for pipelined access to configurable storage blocks.

Abstract translation: 集成电路可以具有可配置的存储块。 多个可配置存储块可以与具有访问给定地址总线的选定的可配置存储块共享一个或多个内部地址总线。 地址总线可以是单向的或双向的，并且可以将相同的地址信号从一个可配置地址块传送到另一个或另一个可配置的存储块。 三态缓冲器或多路复用器可以在可配置存储块之间选择性地耦合或去耦地址总线。 冗余地址总线路径可以绕过相邻行或列中的可配置地址块，允许禁用相应的行或列。 地址总线可以进一步具有流水线寄存器以允许对可配置存储块的流水线访问。

公开(公告)号：US09100011B1

公开(公告)日：2015-08-04

申请号：US14594832

申请日：2015-01-12

Applicant: ALTERA CORPORATION

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway ,  Tim Vanderhoek

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/0944

CPC classification number: H03K19/1737 ,  H03K19/0944

Abstract: One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.

公开(公告)号：US08963581B1

公开(公告)日：2015-02-24

申请号：US13630925

申请日：2012-09-28

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway ,  Tim Vanderhoek

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/1737 ,  H03K19/0944

Abstract: One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及用于流水线直接驱动路由的电路，该电路包括路由多路复用器，触发器和模式多路复用器。 路由多路复用器的输出耦合到模式多路复用器和触发器的输入。 触发器的输出连接到模式多路复用器的另一输入端。 触发器可以直接连接到路由复用器和模式多路复用器，或者在替代实施例中，触发器可以是流水线寄存器池的成员。 另一实施例涉及使用脉冲锁存器的用于流水线直接驱动路由的电路。 其他实施例涉及用于流水线直接驱动路由的方法，其包括逻辑元件和触发器元件之间的逻辑间隔的程度。 另一实施例涉及逻辑阵列块。 还公开了其它实施例，方面和特征。

公开(公告)号：US08912834B2

公开(公告)日：2014-12-16

申请号：US13966038

申请日：2013-08-13

Applicant: Altera Corporation

Inventor： Ajay K. Ravi ,  David Lewis

IPC: H03K3/017 ,  H03K5/156 ,  G06F1/10

CPC classification number: H03K3/017 ,  G06F1/10 ,  H03K5/1565

Abstract: Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.

Abstract translation: 提供支持双边沿时钟的集成电路。 集成电路可以包括产生方波时钟信号的锁相环。 时钟信号可以通过输入输出引脚从片外设备提供。 时钟信号可以通过时钟分配网络路由，以向本地时钟信号提供脉冲发生器，以在时钟沿上升沿和下降沿产生时钟脉冲。 脉冲发生器可以产生由具有公共脉冲宽度的上升和下降时钟沿触发的时钟脉冲，以获得最佳性能。 时钟网络引入的占空比失真可能被最小化以获得最佳性能。 可以使用自适应占空比失真电路来控制时钟缓冲器的上拉/下拉驱动强度，使得本地时钟信号的高时钟相位大约为半个时钟周期。

公开(公告)号：US08896344B1

公开(公告)日：2014-11-25

申请号：US13733985

申请日：2013-01-04

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway

IPC: H03K19/173 ,  G06F17/50 ,  H03K19/177

CPC classification number: H03K19/177 ,  G06F17/5054 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

Abstract translation: 配置具有用户逻辑设计的可编程集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的用户逻辑设计中的单向逻辑路径和在用户逻辑设计内的循环逻辑路径，将循环逻辑路径分配给第一 可编程集成电路器件以第一数据速率工作的部分，将单向逻辑路径分配给可编程集成电路器件的第二部分中的逻辑，该第二部分以低于第一数据速率的第二数据速率工作;以及流水线化单向 可编程集成电路器件的第二部分中的数据路径，以补偿较低的第二数据速率。 适于执行这种方法的可编程集成电路设备可以具有以不同速率操作的逻辑区域，包括具有可编程选择的数据速率的逻辑区域。

公开(公告)号：US20140082035A1

公开(公告)日：2014-03-20

申请号：US14086328

申请日：2013-11-21

Applicant: Altera Corporation

Inventor： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Wai-Bor Leung ,  David Lewis ,  Volker Mauer ,  Henry Y. Lui ,  Suleyman Sirri Demirsoy ,  Hyun Yi

IPC: G06F17/10

CPC classification number: G06F17/10 ,  G06F7/5324 ,  G06F2207/382 ,  H03H17/06 ,  H03H2220/06 ,  H03K19/17732

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract translation: 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

公开(公告)号：US08645885B1

公开(公告)日：2014-02-04

申请号：US13733994

申请日：2013-01-04

Applicant: Altera Corporation

Inventor： Valavan Manohararajah ,  David Galloway ,  David Lewis

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining multithreading characteristics of at least a portion the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, multithreading the at least a portion of the configuration based on the second user input, and retiming the multithreaded configuration.

Abstract translation: 配置具有用户逻辑设计的可编程集成电路器件的方法包括接受定义用户逻辑设计的第一用户输入，接受定义用户逻辑设计的至少一部分的多线程特性的第二用户输入，确定可编程 具有用户逻辑设计的集成电路设备，基于第二用户输入多线程配置的至少一部分，以及重新定时多线程配置。

公开(公告)号：US09824024B1

公开(公告)日：2017-11-21

申请号：US14530576

申请日：2014-10-31

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Jeffrey Christopher Chromczak ,  David Lewis

IPC: G06F12/00 ,  G06F12/1072 ,  G06F12/1009 ,  G06F13/28 ,  G06F12/0875

CPC classification number: G06F13/287 ,  H03K19/1776

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control circuit. The control circuit may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement first-in first-out modules, shift registers, or delay-line modules in addition to implementing memory modules with random access.

公开(公告)号：US09692418B1

公开(公告)日：2017-06-27

申请号：US14464340

申请日：2014-08-20

Applicant: Altera Corporation

Inventor： David Lewis ,  Herman Henry Schmit ,  Carl Ebeling

IPC: H03K19/173 ,  H03K19/0175

CPC classification number: H03K19/017581 ,  H03K19/017509 ,  H03K19/018521 ,  H03K19/1737

Abstract: An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.