公开(公告)号：US10177117B2

公开(公告)日：2019-01-08

申请号：US15133081

申请日：2016-04-19

Applicant: Amkor Technology Inc.

Inventor： Won Bae Bang ,  Ju Hoon Yoon ,  Ji Young Chung ,  Byong Jin Kim ,  Gi Jeong Kim ,  Choon Heung Lee

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/36 ,  H01L23/31 ,  H01L23/00 ,  H01L23/13

Abstract: In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.

公开(公告)号：US20180134546A1

公开(公告)日：2018-05-17

申请号：US15351026

申请日：2016-11-14

Applicant: Amkor Technology, Inc.

Inventor： Ji Hoon Oh ,  Byong Jin Kim ,  Jin Young Kim ,  Young Seok Kim ,  EunNaRa Cho ,  Yung Woo Lee ,  Do Hyun Na

IPC: B81B7/00 ,  B81C1/00

CPC classification number: H01L23/315 ,  B81C1/0023 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/19105 ,  H01L2924/00014

Abstract: Disclosed is a semiconductor device including a conductive shield layer formed within a cavity of a molding part and a manufacturing method thereof. Various aspects of the present invention, for example and without limitation, includes a semiconductor device including a conductive shield layer formed along the wall of a cavity to of a molding part to improve EMI shielding performance, and a manufacturing method thereof.

公开(公告)号：US09871011B2

公开(公告)日：2018-01-16

申请号：US15018635

申请日：2016-02-08

Applicant: Amkor Technology, Inc.

Inventor： Jae Yun Kim ,  Tae Kyung Hwang ,  Jin Han Kim ,  Jong Sik Paek ,  Kyoung Rock Kim ,  Byong Jin Kim ,  Jae Beum Shim

IPC: H01L29/49 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/56 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/03001 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05139 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05578 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/15153 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00012

Abstract: A semiconductor package, and a method of manufacturing thereof, comprising a contact in a plated sidewall encapsulant opening, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

公开(公告)号：US20170320723A1

公开(公告)日：2017-11-09

申请号：US15149669

申请日：2016-05-09

Applicant: Amkor Technology, Inc.

Inventor： Jae Ung Lee ,  Byong Jin Kim ,  Young Seok Kim ,  Wook Choi ,  Seung Jae Yoo ,  Yung Woo Lee ,  EunNaRa Cho ,  Dong Hyun Bang

IPC: B81B3/00 ,  B81C1/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/28 ,  H01L21/56

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  H01L21/568 ,  H01L23/055 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/562 ,  H01L24/83 ,  H01L24/97 ,  H01L25/065 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/16152

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

公开(公告)号：US09716071B2

公开(公告)日：2017-07-25

申请号：US14810664

申请日：2015-07-28

Applicant: Amkor Technology, Inc.

Inventor： Ji Yeon Ryu ,  Byong Jin Kim ,  Jae Beum Shim

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device with fine pitch redistribution layers is disclosed and may include a semiconductor die with a bond pad and a first passivation layer comprising an opening above the bond pad. A redistribution layer (RDL) may be formed on the passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region. A second passivation layer may be formed on the RDL with an opening for the connection region of the RDL. An under bump metal (UBM) may be formed on the connection region of the RDL and a portion of the second passivation layer. A bump contact may be formed on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer and may be constant from the bond pad through at least a portion of the opening.

公开(公告)号：US09552999B2

公开(公告)日：2017-01-24

申请号：US14967293

申请日：2015-12-12

Applicant: Amkor Technology, Inc.

Inventor： Tae Ki Kim ,  Byong Jin Kim ,  Ji Young Chung ,  Gi Jeong Kim ,  Won Bae Bang

IPC: H01L21/48 ,  H01L23/522 ,  H01L23/495 ,  H01L23/64 ,  H01L23/31 ,  H01L23/66 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/4821 ,  H01L21/56 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49861 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13387 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81447 ,  H01L2224/83385 ,  H01L2224/83447 ,  H01L2224/83851 ,  H01L2924/15159 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

Abstract translation: 在一个实施例中，电子封装包括具有芯片焊盘的衬底，多个焊盘嵌入衬底密封剂内。 包括电子部件的电子芯片连接到管芯焊盘。 管芯焊盘配置有从管芯焊盘的顶表面朝向管芯焊盘的底表面延伸的凹槽。 电子部件至少靠近并与凹槽重叠，以增加管芯焊盘和电子部件之间的距离。 在一个实施例中，电子部件包括无源部件，例如电感器。 封装体封装基片的电子芯片和顶面，并进一步设置在凹槽内。 凹槽垫底表面在凹槽下方连续。

公开(公告)号：US20170018493A1

公开(公告)日：2017-01-19

申请号：US15149141

申请日：2016-05-08

Applicant: Amkor Technology, Inc.

Inventor： Jae Ung Lee ,  Yung Woo Lee ,  EunNaRa Cho ,  Dong Hyun Bang ,  Wook Choi ,  KooWoong Jeong ,  Byong Jin Kim ,  Min Chul Shin ,  Ho Jeong Lim ,  Ji Hyun Kim ,  Chang Hun Kim

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15159 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.

Abstract translation: 半导体封装以及半导体封装的制造方法。 作为非限制性示例，本公开的各个方面提供半导体封装及其制造方法，其包括具有第一表面和与第一表面相对的第二表面的基板，并且包括至少一个形成的第一凹部 在从第一表面朝向第二表面的方向上，形成在第一凹部中的多个第一凹陷导电图案和插入到基板的第一凹部中的第一无源元件，并且具有第一电极和第二电极 电连接到多个第一凹槽导电图案。

公开(公告)号：US20170005029A1

公开(公告)日：2017-01-05

申请号：US15173281

申请日：2016-06-03

Applicant: Amkor Technology Inc.

Inventor： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Ji Young Chung

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/565 ,  H01L21/4857 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49861 ,  H01L2224/16 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die.

Abstract translation: 在一个实施例中，半导体封装包括具有细间距的多层封装导电衬底。 多层封装导电基板包括彼此间隔开的导电引线，设置在引线之间的第一密封剂，与多个引线电连接的第一导电层，设置在第一导电层上的导电柱，第二密封剂封装 第一导电层和导电柱，以及与导电柱电连接并暴露在第二密封剂中的第二导电层。 半导体管芯电连接到第二图案化导电层。 第三密封剂至少覆盖半导体管芯。

公开(公告)号：US09508631B1

公开(公告)日：2016-11-29

申请号：US14983937

申请日：2015-12-30

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Jae Min Bae ,  Byong Jin Kim ,  Won Bae Bang

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49544 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: In one embodiment, a semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.

Abstract translation: 在一个实施例中，半导体器件包括限定多个外围边缘段的管芯焊盘。 此外，半导体器件包括以预定布置设置的多个引线和焊盘。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到至少一些引线和焊盘。 芯片焊盘，引线，焊盘和半导体管芯的至少一部分被封装主体封装，芯片焊盘和焊盘的底表面的至少部分暴露在封装的公共外表面中 身体。

公开(公告)号：US09412729B2

公开(公告)日：2016-08-09

申请号：US14456226

申请日：2014-08-11

Applicant: Amkor Technology, Inc.

Inventor： Ji Young Chung ,  Choon Heung Lee ,  Glenn Rinne ,  Byong Jin Kim

IPC: H01L23/02 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/19107 ,  H01L2924/00014

Abstract: A semiconductor package includes a first package comprising a circuit board and a first semiconductor die mounded on the circuit board, and a second package comprising a mounting board. At least one second semiconductor die may be mounted on the mounting board, and one or more leads may be electrically connected to the mounting board and/or the second semiconductor die. An adhesion member may bond the first package to the second package, and an encapsulant may encapsulate the first package and the second package. the circuit board, the mounting board, and the one or more leads may be arranged to surround the first semiconductor die and the second semiconductor die, and the plurality of leads may be electrically connected to the circuit board and to a constant potential or ground, to reduce the effects of external electromagnetic interference upon the semiconductor package.

Abstract translation: 半导体封装包括第一封装，包括电路板和安置在电路板上的第一半导体管芯，第二封装包括安装板。 至少一个第二半导体管芯可以安装在安装板上，并且一个或多个引线可以电连接到安装板和/或第二半导体管芯。 粘合构件可以将第一包装物粘合到第二包装，并且密封剂可以封装第一包装和第二包装。 电路板，安装板和一个或多个引线可以布置成围绕第一半导体管芯和第二半导体管芯，并且多个引线可以电连接到电路板和恒定电位或接地， 以减少外部电磁干扰对半导体封装的影响。