公开(公告)号：US12165959B2

公开(公告)日：2024-12-10

申请号：US17150739

申请日：2021-01-15

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Marcus Boehm ,  Andreas Grassmann ,  Martin Gruber ,  Uwe Schindler

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.

公开(公告)号：US20230402423A1

公开(公告)日：2023-12-14

申请号：US18336067

申请日：2023-06-16

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L24/13 ,  H01L24/43 ,  H01L24/73

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

公开(公告)号：US11715719B2

公开(公告)日：2023-08-01

申请号：US16875531

申请日：2020-05-15

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L24/13 ,  H01L24/43 ,  H01L24/73

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

公开(公告)号：US11710684B2

公开(公告)日：2023-07-25

申请号：US17070427

申请日：2020-10-14

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Martin Gruber ,  Thorsten Meyer ,  Thorsten Scharf ,  Peter Strobel ,  Stefan Woetzel

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L21/54 ,  H01L23/16

CPC classification number: H01L23/49575 ,  H01L21/54 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/49541

Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.

公开(公告)号：US20230178428A1

公开(公告)日：2023-06-08

申请号：US17543199

申请日：2021-12-06

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Fee Hoon Wendy Wong ,  Thomas Behrens ,  Eric Lopez Bonifacio ,  Chau Fatt Chiang ,  Irmgard Escher-Poeppel ,  Giovanni Ragasa Garbin ,  Martin Gruber ,  Tien Shyang Law ,  Mohamad Azian Mohamed Azizi ,  Si Hao Vincent Yeo

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L21/76838 ,  H01L21/563 ,  H01L23/31 ,  H01L21/4839

Abstract: A method includes providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate including an upper surface that includes a first mesa that is elevated from recessed regions, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.

公开(公告)号：US20210111108A1

公开(公告)日：2021-04-15

申请号：US17070427

申请日：2020-10-14

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Martin Gruber ,  Thorsten Meyer ,  Thorsten Scharf ,  Peter Strobel ,  Stefan Woetzel

IPC: H01L23/495 ,  H01L23/16 ,  H01L23/31 ,  H01L21/54 ,  H01L21/56

Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.

公开(公告)号：US10971457B2

公开(公告)日：2021-04-06

申请号：US16382866

申请日：2019-04-12

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.

公开(公告)号：US10964628B2

公开(公告)日：2021-03-30

申请号：US16282207

申请日：2019-02-21

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Bun Kian Tay

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US10168391B2

公开(公告)日：2019-01-01

申请号：US15049923

申请日：2016-02-22

Applicant: Infineon Technologies AG

Inventor： Giuliano Angelo Babulano ,  Jens Oetjen ,  Liu Chen ,  Toni Salminen ,  Stefan Mieslinger ,  Markus Dinkel ,  Martin Gruber ,  Franz Jost ,  Thorsten Meyer ,  Rainer Schaller

IPC: H01L25/16 ,  G01R33/00 ,  G01R33/09 ,  H01L43/08 ,  H01L43/02

Abstract: An interconnect module includes a metal clip having a first end section, a second end section and a middle section extending between the first and the second end sections. The first end section is configured for external attachment to a bare semiconductor die or packaged semiconductor die attached to a carrier or to a metal region of the carrier. The second end section is configured for external attachment to a different metal region of the carrier or to a different semiconductor die or packaged semiconductor die attached to the carrier. The module further includes a magnetic field sensor secured to the metal clip. The magnetic field sensor is operable to sense a magnetic field produced by current flowing through the metal clip. The interconnect module can be used to form a direct electrical connection between components and/or metal regions of a carrier to which the module is attached.

公开(公告)号：US20170271298A1

公开(公告)日：2017-09-21

申请号：US15459151

申请日：2017-03-15

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Andreas Munding ,  Catharina Wille

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/09 ,  H01L24/16 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/095 ,  H01L2224/16104 ,  H01L2224/16112 ,  H01L2224/16137 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.