公开(公告)号：US20200273962A1

公开(公告)日：2020-08-27

申请号：US16649933

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Prashant Majhi ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L27/22 ,  H01L27/24 ,  H01L29/49

Abstract: A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.

公开(公告)号：US10732217B2

公开(公告)日：2020-08-04

申请号：US16073688

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Kevin P. O'Brien ,  Kaan Oguz ,  Christopher J. Wiegand ,  Mark L. Doczy ,  Brian S. Doyle ,  MD Tofizur Rahman ,  Oleg Golonzka ,  Tahir Ghani

IPC: G01R31/28 ,  H01L43/12 ,  G01R33/09 ,  G01R31/315 ,  H01L21/66 ,  G01R33/60 ,  G01N24/10 ,  G01R35/00

Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.

公开(公告)号：US20200235163A1

公开(公告)日：2020-07-23

申请号：US16630924

申请日：2017-09-14

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Abhishek A. Sharma

IPC: H01L27/24 ,  H01L27/22

Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include germanium, tellurium, and sulfur.

公开(公告)号：US10580975B2

公开(公告)日：2020-03-03

申请号：US15753468

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： Mark L. Doczy ,  Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Kevin P. O'Brien ,  Satyarth Suri ,  Tejaswi K. Indukuri

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L27/22

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US20200058646A1

公开(公告)日：2020-02-20

申请号：US16103809

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Brian S. Doyle

IPC: H01L27/06 ,  H01L29/78 ,  H01L27/108 ,  H01L27/11 ,  H01L23/522

Abstract: Disclosed herein are structures and methods for large integrated circuit (IC) dies, as well as related assemblies and devices. For example, in some embodiments, an IC die may include: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.

公开(公告)号：US20190296081A1

公开(公告)日：2019-09-26

申请号：US15934659

申请日：2018-03-23

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

IPC: H01L27/24 ,  H01L45/00 ,  H01L49/00 ,  H01L29/786 ,  H03K19/0944 ,  G11C13/00

Abstract: Selector-based electronic devices, inverters, memory devices, and computing devices include a first selector and a second selector. The first selector and the second selector are electrically connected in series between a first voltage source terminal and a second voltage source terminal. The electronic device also includes a transistor electrically connected between an input terminal and a terminal between the first selector and the second selector.

公开(公告)号：US10340445B2

公开(公告)日：2019-07-02

申请号：US15755446

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/08 ,  H01L43/10 ,  H01F10/30 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.

公开(公告)号：US10340443B2

公开(公告)日：2019-07-02

申请号：US15735613

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Elijah V. Karpov ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Niloy Mukherjee ,  Prashant Majhi

IPC: H01L43/02 ,  H01L43/08 ,  H01L45/00 ,  H01L27/22 ,  H01L43/10

Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.

公开(公告)号：US10326075B2

公开(公告)日：2019-06-18

申请号：US15755437

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01F10/32 ,  H01F41/30 ,  G11C11/16

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.

公开(公告)号：US20190027536A1

公开(公告)日：2019-01-24

申请号：US15767127

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  Kaan Oguz ,  Kevin P. O'Brien ,  Tofizur Rahman ,  Brian S. Doyle ,  Tahir Ghani ,  Mark L. Doczy

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Disclosed herein are electrical contacts for magnetoresistive random access memory (MRAM) devices and related memory structures, devices, and methods. For example, and electrical contact for an MRAM device may include: a tantalum region; a barrier region formed of a first material; and a passivation region formed of a second material and disposed between the tantalum region and the barrier region, wherein the second material includes tantalum nitride and is different from the first material.