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    REMAPPING BAD BLOCKS IN A MEMORY SUB-SYSTEM
    41.
    发明公开
    REMAPPING BAD BLOCKS IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240192875A1

    公开(公告)日：2024-06-13

    申请号：US18519611

    申请日：2023-11-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yang Liu ,  Wenyen Chang ,  Wei Wang ,  Aaron Lee ,  Jiangli Zhu

    IPC: G06F3/06

    CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0679

    Abstract: A system includes a memory device having a plurality of memory planes and a processing device operatively coupled with the memory device. The processing device to is perform operations including identifying a first block stripe of the memory device. The first block stripe includes a first plurality of blocks arranged across the plurality of memory planes. The operations further include determining that the first plurality of blocks of the first block stripe has greater than a threshold number of blocks associated with an error condition. Responsive to determining that the first plurality of blocks has greater than the threshold number of blocks associated with the error condition, the operations further include mapping a block of the first plurality of blocks associated with the error condition to a second block stripe including a second plurality of blocks having fewer than the threshold number of blocks associated with the error condition.

    ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION
    44.
    发明公开
    ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION 审中-公开

    公开(公告)号：US20230393920A1

    公开(公告)日：2023-12-07

    申请号：US17858731

    申请日：2022-07-06

    Applicant: Micron Technology, Inc.

    Inventor： Charles See Yeung Kwong ,  Seungjune Jeon ,  Wei Wang ,  Zhenming Zhou

    IPC: G06F11/07 ,  G06F11/00

    CPC classification number: G06F11/076 ,  G06F11/073 ,  G06F11/008

    Abstract: A set of blocks of a memory device comprising a plurality of dies is identified. A block within the set of blocks is identified. The identified block is associated with a capability metric that reflects a projected reliability of the die on which the block resides. Responsive to determining that the capability metric satisfies a condition, a cycle threshold associated with the die is identified. Responsive to determining that a cycle count value derived from a program/erase cycle counter associated with the die matches the cycle threshold, the set of blocks is updated by excluding the block from the set of blocks. A program operation is performed with respect to the updated set of blocks.

    Power loss recovery for memory devices
    45.
    发明授权
    Power loss recovery for memory devices 有权

    公开(公告)号：US11714722B2

    公开(公告)日：2023-08-01

    申请号：US17486260

    申请日：2021-09-27

    Applicant: Micron Technology, Inc.

    Inventor： Yipei Yu ,  Wei Wang ,  Jiangli Zhu ,  Huapeng Guan

    IPC: G06F11/14

    CPC classification number: G06F11/1446 ,  G06F11/1471 ,  G06F2201/84

    Abstract: An example memory sub-system includes one or more memory devices and a processing device, operatively coupled to the one or more memory devices. The processing device is configured to store, on a non-volatile memory device of the one or more memory devices, a snapshot of a logical-to-physical (L2P) table comprising a plurality of L2P table entries, each L2P table entry mapping a logical address defined in a logical address space to a physical address identifying a management unit on a memory device of the one or more memory devices; store, on the non-volatile memory device of the one or more memory devices, a physical-to-logical (P2L) table comprising a plurality of P2L table entries, each L2P table entry mapping a physical address identifying a management unit on a memory device of the one or more memory devices to metadata associated with the management unit; store, on the non-volatile memory device, a list of unallocated MUs; store, on the non-volatile memory device, an L2P update journal including one or more L2P journal entries, wherein each L2P journal entry reflects an update to an L2P table entry of the plurality of L2P table entries, wherein the update has been performed after storing the snapshot of the L2P table; and responsive to detecting a power up event following a power loss event, reconstruct the L2P table using the snapshot of the L2P table, the L2P update journal, the P2L table, and the list of unallocated management units.

    MANAGING THERMAL THROTTLING IN A MEMORY SUB-SYSTEM
    47.
    发明申请
    MANAGING THERMAL THROTTLING IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20230131347A1

    公开(公告)日：2023-04-27

    申请号：US17507186

    申请日：2021-10-21

    Applicant: Micron Technology, Inc.

    Inventor： Huapeng G. Guan ,  Horia C. Simionescu ,  Jiangli Zhu ,  Venkata Naga Lakshman Pasala ,  Wei Wang

    IPC: G06F3/06

    Abstract: A plurality of temperature values of the memory device is received. A temperature value of the plurality of temperature values that satisfies a thermal throttling threshold of a plurality of thermal throttling thresholds is determined, wherein each thermal throttling threshold of the plurality of thermal throttling thresholds triggers a corresponding thermal throttling state of the memory device. In response to determining that the temperature value satisfies the respective thermal throttling threshold, a thermal throttling operation associated with the corresponding thermal throttling state is performed.

    MANAGING POWER LOSS IN A MEMORY DEVICE
    48.
    发明申请
    MANAGING POWER LOSS IN A MEMORY DEVICE 有权

    公开(公告)号：US20230065617A1

    公开(公告)日：2023-03-02

    申请号：US17464350

    申请日：2021-09-01

    Applicant: Micron Technology, Inc.

    Inventor： Huapeng G. Guan ,  Frederick Adi ,  Jiangli Zhu ,  Yipei Yu ,  Venkata Naga Lakshman Pasala ,  Wei Wang

    IPC: G06F12/0804 ,  G06F12/1009

    Abstract: A system for managing power loss can include a number of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices. The processor can save a snapshot of a logical-to-physical (L2P) table to a non-volatile memory device and maintain a journal of updates of the L2P. The processor can, in response to a parameter of journal buffer of a volatile memory device satisfying a threshold criterion, save at least one journal of updates of the L2P table to the non-volatile memory device. It can also retrieve a sequence number from system metadata and save the most recent set of updates of the L2P table to a dedicated area of the non-volatile memory device, where the dedicated area is identified by the sequence number, in response to detecting a power loss event.

    SCHEDULING COMMAND EXECUTION
    49.
    发明申请
    SCHEDULING COMMAND EXECUTION 有权

    公开(公告)号：US20210019182A1

    公开(公告)日：2021-01-21

    申请号：US16913751

    申请日：2020-06-26

    Applicant: Micron Technology, Inc.

    Inventor： Jason Duong ,  Chih-Kuo Kao ,  Jiangli Zhu ,  Ying Yu Tai ,  Wei Wang

    IPC: G06F9/48 ,  G06F9/38 ,  G06F3/06

    Abstract: Methods, systems, and devices for scheduling command execution are described. A memory sub-system can schedule command execution according to a type of command received. For a read operation, a memory sub-system can receive read commands for multiple memory dice. The memory sub-system can select a first memory die and execute a first set of read commands associated with the first memory die. The memory sub-system can then select a second memory die and execute a second set of read commands associated with the second memory die.

    INTERNAL MANAGEMENT TRAFFIC REGULATION FOR MEMORY SUB-SYSTEMS
    50.
    发明申请
    INTERNAL MANAGEMENT TRAFFIC REGULATION FOR MEMORY SUB-SYSTEMS 有权

    公开(公告)号：US20210019181A1

    公开(公告)日：2021-01-21

    申请号：US16855510

    申请日：2020-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Fangfang Zhu ,  Ying Yu Tai ,  Ning Chen ,  Jiangli Zhu ,  Wei Wang

    IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50 ,  G06F13/16 ,  G06F11/30

    Abstract: Embodiments include methods, systems, devices, instructions, and media for internal management traffic regulation in memory devices. In one embodiment, a processing device is coupled to memory components to monitor host read operations and host write operations from a host device coupled to the plurality of memory components. The processing device schedules, using a variable size internal command queue, a predetermined proportion of back-end processing device read and write operations as internal management traffic proportional to a number of the host read operations and a number of the host write operations. The processing device then executes a subset of the host read operations and the host write operations. Following execution of the subset of the host read operations and the host write operations, the processing device executes an internal management traffic operation based on the predetermined proportion.

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