公开(公告)号：US20240215235A1

公开(公告)日：2024-06-27

申请号：US18092777

申请日：2023-01-03

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Zongliang Huo

IPC: H10B41/40 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40

Abstract: A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a pad-out structure disposed on the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal in contact with the first side of the first semiconductor layer and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; and a plate line extending in the second direction.

公开(公告)号：US20240212753A1

公开(公告)日：2024-06-27

申请号：US18095336

申请日：2023-01-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Zongliang Huo

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.

公开(公告)号：US12020750B2

公开(公告)日：2024-06-25

申请号：US17480821

申请日：2021-09-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu

IPC: H10B41/27 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L23/528 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of memory cells including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The third semiconductor layer is between the second bonding interface and the second peripheral circuit.

公开(公告)号：US20230361030A1

公开(公告)日：2023-11-09

申请号：US17738715

申请日：2022-05-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yuancheng Yang ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/528 ,  H01L27/11578 ,  H01L27/11551

CPC classification number: H01L23/5283 ,  H01L27/11578 ,  H01L27/11551

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a memory stack on the bottom conductive layer, the memory stack comprising a plurality of alternatively arranged dielectric layers and conductive layers; forming an opening penetrating the memory stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and forming a plurality of interconnection structures to electrically connect the bottom conductive layer, the plurality of conductive layers of the memory stack, and the top contact.

公开(公告)号：US20230138205A1

公开(公告)日：2023-05-04

申请号：US17539784

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on all sides of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

公开(公告)号：US20230133595A1

公开(公告)日：2023-05-04

申请号：US17539742

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, a bit line, and a body line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and coupled to a second terminal. The second terminal is another one of the source and the drain. The body line is coupled to the channel portion of the semiconductor body.

公开(公告)号：US20230068995A1

公开(公告)日：2023-03-02

申请号：US17875016

申请日：2022-07-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu ,  Zongliang Huo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: The present disclosure relates to a three-dimensional (3D) memory and a fabrication method thereof. The method includes forming a memory chip on a first substrate, disposing a first semiconductor layer on the memory chip, forming a plurality of first contacts through the first semiconductor layer, forming a first peripheral circuit chip based on the first semiconductor layer, disposing a second semiconductor layer on the first peripheral circuit chip, forming a plurality of second contacts through the second semiconductor layer, and forming a second peripheral circuit chip based on the second semiconductor layer. The first peripheral circuit chip is electrically connected with the memory chip through the plurality of first contacts, and the second peripheral circuit chip is electrically connected with the memory chip through the plurality of first and second contacts.

公开(公告)号：US20230005865A1

公开(公告)日：2023-01-05

申请号：US17587656

申请日：2022-01-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Wei Liu ,  Liang Chen ,  Yanhong Wang ,  Zhiliang Xia ,  Yuancheng Yang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A three-dimensional 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first semiconductor layer and an array of NAND memory strings. The second semiconductor structure is under a second side of the first semiconductor layer. The second side of the first semiconductor layer is opposite to the first side of the first semiconductor layer. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit includes a first transistor in contact with a first side of the second semiconductor layer. The second peripheral circuit includes a second transistor in contact with a second side of the second semiconductor layer. The second side of the second semiconductor layer is opposite to the first side of the second semiconductor layer.

公开(公告)号：US20230005541A1

公开(公告)日：2023-01-05

申请号：US17480821

申请日：2021-09-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  G11C16/10 ,  G11C16/26

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of memory cells including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The third semiconductor layer is between the second bonding interface and the second peripheral circuit.

公开(公告)号：US20220384474A1

公开(公告)日：2022-12-01

申请号：US17459456

申请日：2021-08-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Bingjie Yan ,  Di Wang ,  Cuicui Kong ,  Wenxi Zhou

IPC: H01L27/11582

Abstract: A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers formed on the doped semiconductor layer. The conductive layers include a plurality of word lines, and a drain select gate line. The channel structure extends through the stack structure along a first direction and is in contact with the doped semiconductor layer. The drain select gate line includes a first dielectric layer in contact with the channel structure, and a first polysilicon layer in contact with the first dielectric layer.