公开(公告)号：US20040109215A1

公开(公告)日：2004-06-10

申请号：US10703827

申请日：2003-11-07

Inventor： James A. Hunter

IPC: H01L021/00 ,  G02F001/00 ,  G02B026/00 ,  G02F001/03

CPC classification number: G02B26/0808 ,  B81B2201/045 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/016 ,  B81C2203/0735 ,  B81C2203/0778 ,  H01L27/0611

Abstract: An integrated device including one or more device drivers and a diffractive light modulator monolithically coupled to the one or more driver circuits. The one or more driver circuits are configured to process received control signals and to transmit the processed control signals to the diffractive light modulator. A method of fabricating the integrated device preferably comprises fabricating a front-end portion for each of a plurality of transistors, isolating the front-end portions of the plurality of transistors, fabricating a front-end portion of a diffractive light modulator, isolating the front end portion of the diffractive light modulator, fabricating interconnects for the plurality of transistors, applying an open array mask and wet etch to access the diffractive light modulator, and fabricating a back-end portion of the diffractive light modulator, thereby monolithically coupling the diffractive light modulator and the plurality of transistors.

Abstract translation: 包括一个或多个器件驱动器和单片耦合到所述一个或多个驱动器电路的衍射光调制器的集成器件。 一个或多个驱动器电路被配置为处理接收到的控制信号并将经处理的控制信号传送到衍射光调制器。 一种制造集成器件的方法优选包括制造用于多个晶体管中的每一个晶体管的前端部分，隔离多个晶体管的前端部分，制造衍射光调制器的前端部分，将前部 衍射光调制器的端部，制造用于多个晶体管的互连，施加开放阵列掩模和湿蚀刻以访问衍射光调制器，以及制造衍射光调制器的后端部分，从而将衍射光 调制器和多个晶体管。

公开(公告)号：US20040106221A1

公开(公告)日：2004-06-03

申请号：US10720498

申请日：2003-11-24

Inventor： James A. Hunter ,  Charles B. Roxlo ,  Alexander Payne

IPC: H01L021/00

CPC classification number: G02B26/0808 ,  B81B2201/045 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/016 ,  B81C2203/0735 ,  B81C2203/0778 ,  H01L27/0611

Abstract: An integrated device includes one or more device drivers and a micro-electro-mechanical system (MEMS) structure monolithically coupled to the one or more device drivers. The one or more device drivers are configured to process received control signals and to transmit the processed control signals to the MEMS structure. Methods of fabricating integrated devices are also disclosed.

Abstract translation: 集成器件包括一个或多个器件驱动器和与该一个或多个器件驱动器单片耦合的微机电系统（MEMS）结构。 一个或多个设备驱动器被配置为处理接收的控制信号并将经处理的控制信号传送到MEMS结构。 还公开了制造集成器件的方法。

公开(公告)号：US06605487B2

公开(公告)日：2003-08-12

申请号：US10027044

申请日：2001-12-20

Applicant: Martin Franosch ,  Reinhard Wittmann ,  Catharina Pusch

Inventor： Martin Franosch ,  Reinhard Wittmann ,  Catharina Pusch

IPC: H01L2100

CPC classification number: B81C1/00476 ,  B81C1/00047 ,  B81C2201/016

Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.

公开(公告)号：US20020123232A1

公开(公告)日：2002-09-05

申请号：US09683692

申请日：2002-02-04

Inventor： Tsung-Ping Hsu ,  In-Yao Lee ,  Hung-Sheng Hu ,  Chung-Cheng Chou ,  Wei-Lin Chen

IPC: H01L021/302 ,  H01L021/461

CPC classification number: B81C1/00626 ,  B81C2201/0133 ,  B81C2201/016

Abstract: A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layerand a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.

Abstract translation: 用于高密度晶片生产的渐变蚀刻方法。 分级蚀刻方法分别作用于具有基板的顶表面和底表面上的第一钝化层和第二钝化层的基板上。 执行第一蚀刻工艺以同时蚀刻衬底和第一钝化层以去除第一钝化层。 最后，执行第二蚀刻工艺以将衬底蚀刻到用于在第二蚀刻工艺之后控制晶片的厚度的指定深度。

公开(公告)号：US11905166B2

公开(公告)日：2024-02-20

申请号：US17446898

申请日：2021-09-03

Applicant: Robert Bosch GmbH

Inventor： Heribert Weber ,  Peter Schmollngruber ,  Thomas Friedrich ,  Andreas Scheurle ,  Joachim Fritz ,  Sophielouise Mach

IPC: B81C1/00 ,  B81B3/00 ,  H04R3/00

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/016 ,  B81C2201/0132 ,  H04R3/00

Abstract: A production method for a micromechanical component for a sensor or microphone device. The method includes: patterning a plurality of first trenches through a substrate surface of a monocrystalline substrate made of at least one semiconductor material using anisotropic etching, covering the lateral walls of the plurality of first trenches with a passivation layer, while bottom areas of the plurality of first trenches are kept free or are freed of the passivation layer, etching at least one first cavity, into which the plurality of first trenches opens, into the monocrystalline substrate using an isotropic etching method, in which an etching medium of the isotropic etching method is conducted through the plurality of first trenches, and by covering the plurality of first trenches by epitaxially growing a monocrystalline sealing layer on the substrate surface of the monocrystalline substrate made of the at least one identical semiconductor material as the monocrystalline substrate.

公开(公告)号：US20230312337A1

公开(公告)日：2023-10-05

申请号：US18023904

申请日：2021-09-01

Applicant: 3C PROJECT MANAGEMENT LIMITED

Inventor： Gregory John MCAVOY

IPC: B81B7/02 ,  B41J2/14 ,  H10N30/20 ,  B81C1/00 ,  B41J2/045

CPC classification number: B81C1/00246 ,  B41J2/04581 ,  B41J2/14 ,  B81B7/02 ,  H10N30/20 ,  B81B2201/03 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81B2207/015 ,  B81C2201/0132 ,  B81C2201/016

Abstract: A method of manufacturing a MEMS device, the MEMS device comprising a movable Micro-Electro-Mechanical piezoelectric component and a CMOS circuit configured to be in conductive communication with the Micro-Electro-Mechanical component. A plurality of CMOS circuit layers are formed on a substrate to form the CMOS circuit, the plurality of CMOS circuit layers comprising a plurality of CMOS passivation and metallisation layers. A portion of at least one of the plurality of CMOS passivation and metallisation layers is removed in a component region of the device. One or more component region layers are formed in place of the removed portion in the component region to form the movable Micro-Electro-Mechanical piezoelectric component. The one or more component region layers are different from the portion of the at least one of the plurality of CMOS passivation and metallisation layers.

公开(公告)号：US11708264B2

公开(公告)日：2023-07-25

申请号：US17827437

申请日：2022-05-27

Applicant: SiTime Corporation

Inventor： Pavan Gupta ,  Aaron Partridge ,  Markus Lutz

IPC: B81B7/00 ,  B81C1/00 ,  H10N30/30 ,  H01L23/34 ,  H01L23/498 ,  H01L23/31

CPC classification number: B81B7/0083 ,  B81B7/007 ,  B81B7/0077 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00333 ,  B81C1/00341 ,  H01L23/34 ,  H01L23/498 ,  H10N30/302 ,  B81B2201/0271 ,  B81B2207/07 ,  B81B2207/094 ,  B81C2201/016 ,  B81C2203/0118 ,  B81C2203/0154 ,  H01L23/3107 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

公开(公告)号：US20170029269A1

公开(公告)日：2017-02-02

申请号：US15187748

申请日：2016-06-20

Applicant: SiTime Corporation

Inventor： Pavan Gupta ,  Aaron Partridge ,  Markus Lutz

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0083 ,  B81B7/007 ,  B81B7/0077 ,  B81B2201/0271 ,  B81B2207/07 ,  B81B2207/094 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00333 ,  B81C1/00341 ,  B81C2201/016 ,  B81C2203/0118 ,  B81C2203/0154 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/498 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

Abstract translation: 用于微机电系统（MEMS）谐振器系统的薄型封装结构包括电引线，其具有在封装结构的横截面轮廓内的相应的第一和第二高度处的内部和外部电接触表面，以及模具安装表面 第一和第二高度之间的中间高度。 谐振器控制芯片安装到电引线的管芯安装表面，使得谐振器控制芯片的至少一部分设置在第一和第二高度之间并且引线接合到电气的内部电接触表面 铅。 MEMS谐振器芯片以堆叠的管芯配置安装到谐振器控制芯片，并且电机的谐振器芯片，谐振器控制芯片和内部电接触和管芯安装表面被封装在暴露外部的封装外壳内 电气引线的电接触表面在包装结构的外表面。

公开(公告)号：US20160355398A1

公开(公告)日：2016-12-08

申请号：US14731433

申请日：2015-06-05

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： YAN-DA CHEN ,  WENG YI CHEN ,  CHANG-SHENG HSU ,  KUAN-YU WANG ,  YUAN SHENG LIN

IPC: B81C1/00 ,  B81B7/00 ,  B81B3/00

CPC classification number: H01L21/02107 ,  B81B2207/015 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2201/016

Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.

Abstract translation: 本文提供了一种半导体器件。 半导体器件包括：衬底，其包括MEMS区域及其上的连接区域; 设置在所述连接区域中的所述基板上的电介质层; 设置在所述电介质层上的多晶硅层，其中所述多晶硅层用作蚀刻停止层; 设置在所述多晶硅层上的连接焊盘; 以及覆盖所述电介质层的钝化层，其中所述钝化层包括暴露所述连接焊盘的开口和所述连接焊盘与所述钝化层之间的过渡区域。

公开(公告)号：US09371221B2

公开(公告)日：2016-06-21

申请号：US14597825

申请日：2015-01-15

Applicant: SiTime Corporation

Inventor： Pavan Gupta ,  Aaron Partridge ,  Markus Lutz

IPC: H01L23/48 ,  B81B7/00 ,  B81C1/00 ,  H01L23/34 ,  H01L23/498 ,  H01L23/31

CPC classification number: B81B7/0083 ,  B81B7/007 ,  B81B7/0077 ,  B81B2201/0271 ,  B81B2207/07 ,  B81B2207/094 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00333 ,  B81C1/00341 ,  B81C2201/016 ,  B81C2203/0118 ,  B81C2203/0154 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/498 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

Abstract translation: 用于微机电系统（MEMS）谐振器系统的薄型封装结构包括电引线，其在封装结构的横截面轮廓内的相应的第一和第二高度处具有内部和外部电接触表面，并且模具安装表面 第一和第二高度之间的中间高度。 谐振器控制芯片安装到电引线的管芯安装表面，使得谐振器控制芯片的至少一部分设置在第一和第二高度之间并且引线接合到电气的内部电接触表面 铅。 MEMS谐振器芯片以堆叠的管芯配置安装到谐振器控制芯片，并且电机的谐振器芯片，谐振器控制芯片和内部电接触和管芯安装表面被封装在暴露外部的封装外壳内 电气引线的电接触表面在包装结构的外表面。