公开(公告)号：US20140240934A1

公开(公告)日：2014-08-28

申请号：US14271959

申请日：2014-05-07

Applicant: Invensas Corporation

Inventor： Tomoo Iijima ,  Yoshitaka Fukuoka

IPC: H05K1/18

CPC classification number: H05K3/4007 ,  H01L23/498 ,  H01L23/49833 ,  H01L24/19 ,  H01L2924/14 ,  H05K1/0393 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/182 ,  H05K1/187 ,  H05K1/189 ,  H05K3/06 ,  H05K3/205 ,  H05K3/46 ,  H05K3/4614 ,  H05K3/4635 ,  H05K3/4652 ,  H05K2201/0367 ,  H05K2203/0384 ,  Y10T29/49155 ,  H01L2924/00

Abstract: An electronic assembly is disclosed that includes a flexible insulating film, a semiconductor component that has a thickness of less than 50 micrometers, a conductive interconnect extending through the flexible insulating film, a second patterned metal wiring film adjacent, and a third patterned metal wiring film. The second patterned metal wiring film is electrically coupled with the third patterned metal wiring film through the conductive interconnect. The semiconductor component is coupled to the first patterned metal wiring film and at least one of the second patterned metal wiring film or the third patterned metal wiring film.

Abstract translation: 公开了一种电子组件，其包括柔性绝缘膜，厚度小于50微米的半导体部件，延伸穿过柔性绝缘膜的导电互连，邻近的第二图案化金属布线膜和第三图案化金属布线膜 。 第二图案化金属布线膜通过导电互连与第三图案化金属布线膜电耦合。 半导体元件耦合到第一图案化金属布线膜和第二图案化金属布线膜或第三图案化金属布线膜中的至少一个。

公开(公告)号：US08817485B2

公开(公告)日：2014-08-26

申请号：US12603324

申请日：2009-10-21

Applicant: Risto Tuominen ,  Petteri Palm

Inventor： Risto Tuominen ,  Petteri Palm

IPC: H05K1/18 ,  H05K7/12

CPC classification number: H05K1/188 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/552 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0269 ,  H05K3/4611 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/00

Abstract: A single-layer component package comprising: a single conductive-pattern layer having a first surface; an insulating-material layer on the first surface of the single conductive-pattern layer; in an installation cavity inside the insulating-material layer, a semiconductor component having flat contact zones; and solid contact pillars containing copper and solderlessly, metallurgically and electrically connecting the flat contact zones to the single conductive-pattern layer.

Abstract translation: 一种单层部件封装，包括：具有第一表面的单个导电图案层; 在单个导电图案层的第一表面上的绝缘材料层; 在绝缘材料层内的安装空腔中，具有平坦的接触区域的半导体部件; 以及包含铜和无焊料的固体接触柱，将扁平接触区冶金和电连接到单个导电图案层。

公开(公告)号：US20140202748A1

公开(公告)日：2014-07-24

申请号：US14226584

申请日：2014-03-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Myung Sam KANG ,  Jeong Woo PARK ,  Ok Tae KIM ,  Kil Yong YUN

IPC: H05K1/11 ,  H05K1/09

CPC classification number: H05K1/111 ,  H05K1/09 ,  H05K1/115 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0323 ,  H05K2203/0376 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: A printed circuit board includes an upper circuit layer including a circuit pattern embedded in an upper part of an insulating layer, the circuit pattern being made of electroconductive metal; and a metal bump formed on the circuit pattern and the insulating layer

Abstract translation: 印刷电路板包括上电路层，其包括嵌入在绝缘层的上部的电路图案，所述电路图案由导电金属制成; 以及形成在电路图案和绝缘层上的金属凸块

公开(公告)号：US08785789B2

公开(公告)日：2014-07-22

申请号：US13402638

申请日：2012-02-22

Applicant: Hueng Jae Oh ,  Boo Yang Jung ,  Dae Young Lee ,  Jin Won Choi

Inventor： Hueng Jae Oh ,  Boo Yang Jung ,  Dae Young Lee ,  Jin Won Choi

IPC: H05K1/11 ,  H01K3/10

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/1184 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/8138 ,  H01L2224/81801 ,  H01L2224/831 ,  H05K1/111 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09845 ,  H05K2203/054 ,  H05K2203/0588 ,  Y02P70/611 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Disclosed herein are a printed circuit board (PCB) and a method for manufacturing the same. The PCB includes a base substrate, a circuit layer formed on the base substrate and including a connection pad, a solder resist layer formed on an upper portion of the base substrate and having an opening exposing the connection pad, a metal post formed on upper portions of the connection pad and the solder resist layer and having a plurality of diameters, and a seed layer formed on the upper portion of the solder resist layer and inner walls of the opening along an interface of the metal post.

Abstract translation: 这里公开了印刷电路板（PCB）及其制造方法。 PCB包括基底基板，形成在基底基板上的电路层，包括连接焊盘，形成在基底基板的上部上并具有露出连接焊盘的开口的阻焊层，形成在上部的金属柱 的连接焊盘和阻焊层，并且具有多个直径，以及沿着金属柱的界面形成在阻焊层的上部和开口的内壁上的种子层。

公开(公告)号：US08749073B2

公开(公告)日：2014-06-10

申请号：US13154565

申请日：2011-06-07

Applicant: Junichi Nakamura ,  Kentaro Kaneko ,  Shunichiro Matsumoto

Inventor： Junichi Nakamura ,  Kentaro Kaneko ,  Shunichiro Matsumoto

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/16 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19101 ,  H01L2924/19105 ,  H05K1/111 ,  H05K3/244 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/10015 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/308

Abstract: A wiring board includes a structure in which a plurality of wiring layers are stacked with insulating layers interposed therebetween, a plurality of pads for mounting an electronic component, the pads being formed on an outermost insulating layer on one surface side of the structure and exposed to the surface of the outermost insulating layer, and a recessed portion formed at a place corresponding to a mounting area for the electronic component. The recessed portion is formed in the outermost insulating layer at an area between the pads to which electrode terminals of the electronic component to be mounted are to be connected, respectively.

Abstract translation: 布线基板包括多个布线层层叠有绝缘层的结构，多个用于安装电子部件的焊盘，该焊盘形成在该结构的一个表面侧上的最外侧的绝缘层上并暴露于 最外层绝缘层的表面和形成在与电子部件的安装区域对应的位置的凹部。 凹陷部分分别形成在要连接的电子部件的电极端子的焊盘之间的区域中的最外层绝缘层中。

公开(公告)号：US08729406B2

公开(公告)日：2014-05-20

申请号：US12559449

申请日：2009-09-14

Applicant: Young Gwan Ko

Inventor： Young Gwan Ko

IPC: H05K1/11

CPC classification number: H05K1/114 ,  H05K3/0097 ,  H05K3/107 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2203/1536

Abstract: Disclosed is a printed circuit board, which includes an insulating member having a circuit pattern embedded in one surface thereof, a bump pad formed in the insulating member so as to be connected to the circuit pattern and protruding from an outer surface of the insulating member, a build-up layer formed on one surface of the insulating member and including a build-up insulating layer and a circuit layer formed in the build-up insulating layer and having a via connected to the circuit pattern, and a solder resist layer formed on the build-up layer. A method of fabricating the printed circuit board is also provided. The printed circuit board is fabricated using a build-up process and the outermost circuit layer thereof is formed to have an embedded structure using an imprinting process, thus minimizing the separation of the circuit layer and reducing the lead time and the fabrication cost.

Abstract translation: 公开了一种印刷电路板，其包括具有嵌入其一个表面中的电路图案的绝缘构件，形成在所述绝缘构件中以与所述电路图案连接并从所述绝缘构件的外表面突出的凸块焊盘， 形成在所述绝缘构件的一个表面上并包括积聚绝缘层和形成在所述积层绝缘层中并且具有连接到所述电路图案的通孔的电路层的堆积层，以及形成在所述绝缘层上的阻焊层 积层。 还提供了制造印刷电路板的方法。 印刷电路板使用积聚工艺制造，并且其最外面的电路层被形成为具有使用压印工艺的嵌入式结构，从而最小化电路层的分离并减少了交货时间和制造成本。

公开(公告)号：US20140084475A1

公开(公告)日：2014-03-27

申请号：US13624548

申请日：2012-09-21

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Abstract translation: 衬底包括第一介电层，第一电路图案，多个柱和第二电路图案。 第一电介质层具有相对的第一和第二电介质表面。 第一电路图案嵌入在第一电介质层中并且限定多个弯曲迹线表面。 每个支柱具有适于制造外部电连接的外表面和与相应的一个轨迹表面邻接的弯曲基底表面。 第二电路图案在第一电介质层的第二电介质表面上并且电连接到第一电路图案。

公开(公告)号：US20140042622A1

公开(公告)日：2014-02-13

申请号：US13572417

申请日：2012-08-10

Applicant: Tsai-Tsung Tsai ,  Chun-Cheng Lin ,  Ai-Tee Ang ,  Yi-Da Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Tsai-Tsung Tsai ,  Chun-Cheng Lin ,  Ai-Tee Ang ,  Yi-Da Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15321 ,  H05K3/3436 ,  H05K3/4015 ,  H05K2201/0367 ,  H01L2224/0401

Abstract: A package-on-package (PoP) device including a substrate having an array of contact pads arranged around a periphery of the substrate, a logic chip mounted to the substrate inward of the array of contact pads, and non-solder bump structures mounted on less than an entirety of the contact pads available.

Abstract translation: 一种封装封装（PoP）器件，包括具有围绕衬底的周边布置的接触焊盘阵列的衬底，安装到衬底内部的接触焊盘阵列的逻辑芯片以及安装在衬底上的非焊料凸块结构 小于可用的接触垫的整体。

公开(公告)号：US08641913B2

公开(公告)日：2014-02-04

申请号：US11717587

申请日：2007-03-13

Applicant: Belgacem Haba ,  Yoichi Kubota ,  Teck-Gyu Kang ,  Jae M. Park

Inventor： Belgacem Haba ,  Yoichi Kubota ,  Teck-Gyu Kang ,  Jae M. Park

IPC: H01L21/302

CPC classification number: H01L24/14 ,  H01L21/4828 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/061 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0369 ,  H05K2203/0597 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T428/24174 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method includes applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with the substrate and projecting upwardly from a surface of the substrate, and etching the surface of the substrate so as to leave second microcontact portions below the first microcontact portions and integral therewith, the final etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step. A microelectronic unit includes a substrate, and a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region remote from the substrate, each microcontact having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract translation: 一种方法包括将最终的耐蚀刻材料施加到工艺衬底，使得最终耐蚀刻材料至少部分地覆盖与衬底成一体的第一微接触部分并从衬底的表面向上突出，并且蚀刻表面 衬底，以便将第二微接触部分留在第一微接触部分下方并与之成一体，最后的抗蚀刻材料在另外的蚀刻步骤期间至少部分地保护第一微接触部分免受蚀刻。 微电子单元包括衬底以及从衬底沿垂直方向突出的多个微接点，每个微接触器包括邻近衬底的基极区域和远离衬底的尖端区域，每个微接触体具有作为第一功能的水平尺寸 在基部区域中垂直位置，并且其是尖端区域中垂直位置的第二函数。

公开(公告)号：US20140017938A1

公开(公告)日：2014-01-16

申请号：US13935292

申请日：2013-07-03

Applicant: PANASONIC CORPORATION

Inventor： Hiroshi IWANO ,  Mitsuru IIDA ,  Daisuke SATO ,  Hidetoshi TAKEYAMA

IPC: H01R12/61

CPC classification number: H01R12/613 ,  H01R12/79 ,  H05K1/11 ,  H05K1/114 ,  H05K1/117 ,  H05K3/0038 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09409 ,  H05K2201/09427 ,  H05K2201/09445 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10189 ,  H05K2201/2009 ,  H05K2201/2072 ,  H05K2203/167

Abstract: A socket (female connector) used for a connector assembly includes a film substrate constituted by a flexible thin board made of insulation material. The film substrate is provided with connection through holes adapted to be inserted therein connection posts of a header (male connector). Connection pads are formed on a first surface of the film substrate around respective connection through holes. The connection pads include a first pad and a second pad. The film substrate is provided on the first surface with a first patterned conductor connected to the first pad and a third patterned conductor connected to the second pad. The third patterned conductor is connected to a second patterned conductor formed on a second surface of the film substrate by means of a blind via that is formed by boring the film substrate from the second surface so as to reach the third patterned conductor.

Abstract translation: 用于连接器组件的插座（母连接器）包括由绝缘材料制成的柔性薄板构成的薄膜基片。 薄膜基片设置有适于插入插头（公连接器）的连接柱中的连接通孔。 连接衬垫围绕各个连接通孔形成在薄膜基片的第一表面上。 连接焊盘包括第一焊盘和第二焊盘。 薄膜基板在第一表面上设置有连接到第一焊盘的第一图案化导体和连接到第二焊盘的第三图案化导体。 第三图案化导体通过盲孔通过第二图案导体连接到形成在膜基板的第二表面上的第二图案化导体，所述盲孔通过从第二表面镗孔而形成，以到达第三图案化导体。