公开(公告)号：US20140182905A1

公开(公告)日：2014-07-03

申请号：US14143475

申请日：2013-12-30

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kyung Moo HAR ,  Chang Bae LEE ,  Jin Gu KIM ,  Young Do KWEON

IPC: H05K13/00 ,  H05K1/09

CPC classification number: H05K1/09 ,  H05K3/247 ,  H05K3/3484 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2203/043 ,  H05K2203/0557 ,  H05K2203/081

Abstract: Disclosed herein are a printed circuit board including a copper foil layer surface treated with Pb-free solder having the same height as that of a solder resist, and a surface treatment method of the printed circuit board.According to the present invention, the surface treatment of the package board or interposer board having an ultra-fine pitch (300 μm or less) may be easily implemented by a cheap process. In addition, the surface treatment of the printed circuit board may be eco-friendly performed by using the Pb-free solder, and it may be easy to surface treat the package board or interposer board based on the organic material sensitive to a high temperature.

Abstract translation: 本发明公开了一种印刷电路板，其包括利用与阻焊剂相同高度的无铅焊料处理的铜箔层表面和印刷电路板的表面处理方法。 根据本发明，可以通过廉价的处理容易地实现具有超细间距（300μm以下）的封装基板或中介板的表面处理。 此外，印刷电路板的表面处理可以通过使用无铅焊料进行环保处理，并且可以容易地基于对高温敏感的有机材料来表面处理封装板或插入板。

公开(公告)号：US20140144682A1

公开(公告)日：2014-05-29

申请号：US13891888

申请日：2013-05-10

Applicant: RF MICRO DEVICES, INC.

Inventor： John August Orlowski ,  Donald Joseph Leahy

IPC: H05K1/09 ,  H05K3/00

CPC classification number: H05K3/00 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2924/181 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2203/073 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047

Abstract: An electronic substrate includes one or more conductive features. In order to preserve the performance and conductivity of the one or more conductive features, the exposed portions of the conductive features are deposited with a protective layer comprising a layer of silver, followed by a layer of gold. By covering the exposed portions of the conductive features of the electronic substrate with the protective layer, oxidation and exposure of the conductive features is prevented, thereby preserving the performance and conductivity of the copper features. Further, during a soldering process, the protective layer is substantially dissolved, thereby allowing the solder to join directly with the underlying conductive features and improving the performance of the electronic substrate.

Abstract translation: 电子基板包括一个或多个导电特征。 为了保持一个或多个导电特征的性能和导电性，导电特征的暴露部分被沉积有包含一层银的保护层，随后是一层金。 通过用保护层覆盖电子基板的导电特征的暴露部分，防止导电特征的氧化和曝光，从而保持铜特征的性能和导电性。 此外，在焊接工艺期间，保护层基本上溶解，从而允许焊料直接与下面的导电特征相结合并且改善了电子衬底的性能。

公开(公告)号：US20140054077A1

公开(公告)日：2014-02-27

申请号：US13994253

申请日：2012-10-18

Applicant: Panasonic Corporation

Inventor： Masanori Minamio ,  Hiroki Ikeuchi

IPC: H05K1/03

CPC classification number: H05K1/0306 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49861 ,  H01L23/49894 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0201 ,  H05K1/0203 ,  H05K1/0209 ,  H05K1/0224 ,  H05K1/0256 ,  H05K1/0373 ,  H05K1/186 ,  H05K3/284 ,  H05K3/285 ,  H05K3/4676 ,  H05K2201/0227 ,  H05K2201/0376 ,  H05K2201/0723 ,  H05K2201/1056 ,  H05K2201/10969 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is a resin package structure including a semiconductor element T1 molded with a first resin 6. The first resin 6 contains a filler 7 including an electrical insulating capsule enclosed with a phase-change-material that absorbs ambient heat and phase-changes so as to increase a dielectric-strength. The effect of the filler 7 achieves a structure with satisfactory heat dissipation and a high withstand voltage.

Abstract translation: 半导体器件是包括用第一树脂6模制的半导体元件T1的树脂封装结构。第一树脂6包含填充物7，填充物7包括用相变材料包围的电绝缘胶囊，其吸收周围热量和相变 以提高介电强度。 填料7的效果达到具有令人满意的散热和高耐受电压的结构。

公开(公告)号：US20140014401A1

公开(公告)日：2014-01-16

申请号：US13547454

申请日：2012-07-12

Applicant: Pen-Yi LIAO ,  Ming-Chun WU ,  I-Lin TSENG ,  Tsung-Han WU ,  Jung-Chi LIN

Inventor： Pen-Yi LIAO ,  Ming-Chun WU ,  I-Lin TSENG ,  Tsung-Han WU ,  Jung-Chi LIN

IPC: H05K1/09 ,  H05K3/00

CPC classification number: H05K3/184 ,  H05K3/107 ,  H05K2201/0376 ,  H05K2203/0713 ,  H05K2203/107

Abstract: A circuit device includes: a substrate having an insulative upper surface; a hydrophobic anti-plating layer of a hydrophobic material formed on the upper surface of the substrate and having at least one patterned through-hole for exposing a plating portion of the upper surface of the substrate; an active metal layer formed on the plating portion of the upper surface of the substrate and disposed in the patterned through-hole in the hydrophobic anti-plating layer; and an electroless deposited metal layer electroless deposited on the active metal layer.

Abstract translation: 电路装置包括：具有绝缘上表面的基板; 疏水性材料的疏水性防镀层形成在所述基板的上表面上并且具有至少一个图案化的通孔，用于暴露所述基板的上表面的镀层部分; 形成在所述基板的上表面的电镀部上并设置在所述疏水性防镀层的所述图案化通孔中的活性金属层; 以及沉积在活性金属层上的无电沉积金属层。

公开(公告)号：US08551271B2

公开(公告)日：2013-10-08

申请号：US11924408

申请日：2007-10-25

Applicant: Jerry Ok ,  Robert J. Greenberg

Inventor： Jerry Ok ,  Robert J. Greenberg

IPC: C03B29/00 ,  B29C65/00 ,  H01B13/00

CPC classification number: H05K3/4061 ,  B32B37/14 ,  C04B35/10 ,  C04B37/00 ,  C04B2237/064 ,  H05K1/0306 ,  H05K3/0044 ,  H05K3/0047 ,  H05K3/005 ,  H05K3/12 ,  H05K3/1225 ,  H05K3/1233 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/4629 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2203/1147 ,  H05K2203/308 ,  Y10T156/10

Abstract: A method for fabricating a hermetically sealed electrical feedthrough. The method provides a ceramic sheet and forming at least one via hole in the ceramic sheet, inserting a conductive thickfilm paste into the via hole, laminating the ceramic sheet that has a paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to form an integral ceramic substrate, firing the laminated ceramic substrate to sinter the ceramic substrate and cause the paste filled via hole to form a metalized via while the laminated ceramic substrate form a hermetic seal around the metalized via. The upper ceramic sheet and the lower ceramic sheet are removed from the fired ceramic substrate to expose the upper and lower surface of the metalized via.

Abstract translation: 一种用于制造密封电馈电的方法。 该方法提供陶瓷片并在陶瓷片中形成至少一个通孔，将导电厚膜糊剂插入通孔中，将在上陶瓷片和下陶瓷片之间填充有通孔的陶瓷片层压到 形成整体的陶瓷基板，烧结层叠陶瓷基板以烧结陶瓷基板，并使填充通孔的浆料形成金属化通孔，同时层压陶瓷基板在金属化通孔周围形成气密封。 将上陶瓷片和下陶瓷片从烧制的陶瓷基片上除去，露出金属化通孔的上表面和下表面。

公开(公告)号：US20130255858A1

公开(公告)日：2013-10-03

申请号：US13437933

申请日：2012-04-03

Applicant: Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC: B32B38/10 ,  B32B38/08

CPC classification number: H05K3/282 ,  H05K1/0366 ,  H05K3/103 ,  H05K3/146 ,  H05K3/16 ,  H05K3/202 ,  H05K3/244 ,  H05K3/381 ,  H05K3/384 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2203/0152 ,  H05K2203/0278 ,  H05K2203/072 ,  Y10T156/10

Abstract: A method of manufacturing a laminate circuit board is disclosed. The method includes forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer with a thickness of 5 to 40 nm over the circuit metal layer, and forming a cover layer covering the substrate and the nanometer plating layer with improved adhesion by chemical bonding to form the laminate circuit board. Another method includes forming the circuit metal layer and the nanometer plating layer on a preforming substrate, pressing the preforming substrate against a substrate to push the circuit metal layer and the nanometer plating layer into the substrate, and removing the preforming substrate. By the present invention, the density of circuit is increased and much denser circuit can be implemented on the substrate with the same area.

Abstract translation: 公开了一种制造叠层电路板的方法。 该方法包括在基板上形成金属层，图案化金属层以形成电路金属层，在电路金属层上形成厚度为5至40nm的纳米电镀层，并形成覆盖基板的覆盖层和 纳米电镀层通过化学键合具有改善的粘附性以形成层压电路板。 另一种方法包括在预成型基板上形成电路金属层和纳米电镀层，将预成型基板压靠在基板上，将电路金属层和纳米电镀层推入基板，以及去除预成形基板。 通过本发明，电路的密度增加，并且可以在具有相同面积的基板上实现更加密集的电路。

公开(公告)号：US20130200522A1

公开(公告)日：2013-08-08

申请号：US13836706

申请日：2013-03-15

Applicant: PANASONIC CORPORATION

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA

IPC: H01L23/00

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of mounting a semiconductor chip includes: forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; depositing a plating catalyst on a surface of the wiring gutter; removing the resin coating; and forming an electroless plating coating only at a site where the plating catalyst remains.

Abstract translation: 安装半导体芯片的方法包括：在连接半导体芯片的表面上的接合焊盘和形成在绝缘基材的表面上的电极焊盘的路径的表面上形成树脂涂层; 通过激光束加工形成具有等于或大于沿着用于连接焊盘和电极焊盘的路径的树脂涂层的厚度的深度的布线槽; 在布线槽的表面上沉积电镀催化剂; 去除树脂涂层; 并且仅在电镀催化剂保留的部位形成化学镀层。

公开(公告)号：US20130187182A1

公开(公告)日：2013-07-25

申请号：US13749096

申请日：2013-01-24

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Shigetsugu MURAMATSU ,  Hiroshi SHIMIZU ,  Kazutaka KOBAYASHI

IPC: H01L33/60 ,  H05K3/10

CPC classification number: H01L33/60 ,  H01L25/0753 ,  H01L2224/13 ,  H01L2924/0002 ,  H05K1/0274 ,  H05K3/0014 ,  H05K3/0061 ,  H05K3/10 ,  H05K3/205 ,  H05K2201/0195 ,  H05K2201/0376 ,  H05K2201/09409 ,  H05K2201/10106 ,  H05K2201/2054 ,  Y10T29/49155 ,  H01L2924/00

Abstract: There is provided a wiring substrate. The wiring substrate includes: a heat sink; an insulating member on the heat sink; a wiring pattern embedded in the insulating member and including a first surface and a second surface opposite to the first surface, the second surface contacting the insulating member; and a metal layer on the first surface of the wiring pattern, wherein an exposed surface of the metal layer is flush with an exposed surface of the insulating member.

Abstract translation: 提供了布线基板。 布线基板包括：散热器; 散热器上的绝缘构件; 布线图案，其嵌入在所述绝缘构件中并且包括与所述第一表面相对的第一表面和第二表面，所述第二表面接触所述绝缘构件; 以及在所述布线图案的第一表面上的金属层，其中所述金属层的暴露表面与所述绝缘构件的暴露表面齐平。

公开(公告)号：US08482137B2

公开(公告)日：2013-07-09

申请号：US13144112

申请日：2010-01-26

Applicant: Shingo Yoshioka ,  Hiroaki Fujiwara

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara

IPC: H01L23/48

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One aspect of the present invention is a method of mounting a semiconductor chip having: a step of forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; a step of forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; a step of depositing a plating catalyst on a surface of the wiring gutter; a step of removing the resin coating; and a step of forming an electroless plating coating only at a site where the plating catalyst remains. Another aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, wherein, on the surface of the three-dimensional structure, a recessed gutter for wiring is formed, extending between mutually intersecting adjacent faces of the three-dimensional structure, and wherein at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Abstract translation: 本发明的一个方面是一种安装半导体芯片的方法，该半导体芯片具有：在连接半导体芯片的表面上的接合焊盘的表面上形成树脂涂层的步骤和形成在半导体芯片的表面上的电极焊盘 绝缘基材; 通过激光束加工形成具有等于或大于沿着用于连接焊盘和电极焊盘的路径的树脂涂层的厚度的深度的布线槽的步骤; 将电镀催化剂沉积在布线槽的表面上的步骤; 去除树脂涂层的步骤; 以及仅在电镀催化剂保留的部位形成化学镀镀层的工序。 本发明的另一方面是其中在表面上形成布线的三维结构，其中在三维结构的表面上形成用于布线的凹槽，在相互相交的相邻面之间延伸 三维结构，并且其中布线导体的至少一部分嵌入到凹槽中用于布线。

公开(公告)号：US20130126224A1

公开(公告)日：2013-05-23

申请号：US13682505

申请日：2012-11-20

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Joon Sung Kim

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/06

CPC classification number: H05K1/11 ,  H05K3/06 ,  H05K3/3452 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4661 ,  H05K2201/0376 ,  H05K2203/1476 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a base substrate; an outer circuit layer formed on an upper portion of the base substrate and including a connection pad; a first solder resist formed on the upper portion of the base substrate so that the connection pad of the outer circuit layer is exposed; and a second solder resist formed on an upper portion of an outer circuit layer and formed so that the connection pad is exposed.

Abstract translation: 这里公开了一种印刷电路板及其制造方法。 印刷电路板包括：基底; 形成在所述基底基板的上部并且包括连接垫的外部电路层; 形成在所述基底基板的上部的第一阻焊膜，使得所述外电路层的所述连接焊盘露出; 以及形成在外部电路层的上部并形成为使得连接焊盘露出的第二阻焊剂。