公开(公告)号：US08607445B1

公开(公告)日：2013-12-17

申请号：US13517776

申请日：2012-06-14

Applicant: Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin

Inventor： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin

IPC: H05K3/30

CPC classification number: H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/107 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/066

Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.

Abstract translation: 一种制造电路化衬底的方法，其包括至少一个可能的几个电容器作为其一部分。 在一个实施例中，通过在电介质层上形成电容电介质材料层，然后用电容材料形成通道，例如使用激光来制造衬底。 然后使用所选择的沉积技术，例如溅射，无电镀和电镀，用导电材料（例如铜）填充通道。 然后在电容器顶部形成第二电介质层，并产生电容器“芯”。 然后，该“芯”可以与其它电介质层和导电层组合以形成较大的多层PCB或芯片载体。 在替代方法中，电容介电材料可以是可光成像的，其中通道是使用本领域已知的常规曝光和显影处理形成的。

公开(公告)号：US20130323973A1

公开(公告)日：2013-12-05

申请号：US13746386

申请日：2013-01-22

Applicant: ADC GmbH

Inventor： David Patrick Murray ,  Bernard Harold Hammond, JR.

IPC: H01R13/6466

CPC classification number: H01R13/6466 ,  H01R13/6461 ,  H01R13/6464 ,  H01R13/6658 ,  H01R13/6691 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/53209

Abstract: Methods and systems for providing crosstalk compensation in a jack are disclosed. According to one method, the crosstalk compensation is adapted to compensate for undesired crosstalk generated at a capacitive coupling located at a plug inserted within the jack. The method includes positioning a first capacitive coupling a first time delay away from the capacitive coupling of the plug, the first capacitive coupling having a greater magnitude and an opposite polarity as compared to the capacitive coupling of the plug. The method also includes positioning a second capacitive coupling at a second time delay from the first capacitive coupling, the second time delay corresponding to an average time delay that optimizes near end crosstalk. The second capacitive coupling has generally the same overall magnitude but an opposite polarity as compared to the first capacitive coupling, and includes two capacitive elements spaced at different time delays from the first capacitive coupling.

Abstract translation: 公开了一种用于在千斤顶中提供串扰补偿的方法和系统。 根据一种方法，串扰补偿适于补偿位于插入插座内的插头处的电容耦合处产生的不期望的串扰。 该方法包括将第一时间延迟定位成离开插头的电容耦合的第一电容耦合，与插头的电容耦合相比，第一电容耦合具有更大的幅度和相反的极性。 该方法还包括在第一时间延迟从第一电容耦合定位第二电容耦合，第二时间延迟对应于优化近端串扰的平均时间延迟。 第二电容耦合具有与第一电容耦合相比具有相同的总体幅度但具有相反的极性，并且包括以与第一电容耦合不同的时间延迟隔开的两个电容元件。

公开(公告)号：US08553102B2

公开(公告)日：2013-10-08

申请号：US12703445

申请日：2010-02-10

Applicant: Motonari Yamada

Inventor： Motonari Yamada

IPC: H04N5/228

CPC classification number: H05K1/0216 ,  H05K1/0245 ,  H05K1/147 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10189 ,  H05K2201/10734

Abstract: An electronic apparatus that can prevent occurrence of crosstalk between different differential signals on a printed circuit board on which a wiring pattern of a differentially operated signal line is formed, and reduce unnecessary radiation noises. First and second wiring patterns are disposed on the printed circuit board and through which differentially operated signals are transmitted, and the first and second wiring patterns are electrically connected to first and second connection terminals, respectively. An electronic component is disposed on the printed circuit board, and includes first and second terminals electrically connected to the first and second wiring patterns, respectively. The first and second terminals of the electronic component are disposed on the printed circuit board, respectively, so that the first and second wiring patterns do not intersect each other.

Abstract translation: 能够防止形成差动信号线的布线图案的印刷电路板上的差分信号之间发生串扰的电子设备，并减少不必要的辐射噪声。 第一布线图案和第二布线图案布置在印刷电路板上并通过其传输差分操作的信号，并且第一和第二布线图案分别电连接到第一和第二连接端子。 电子部件设置在印刷电路板上，并且分别包括电连接到第一和第二布线图案的第一和第二端子。 电子部件的第一端子和第二端子分别设置在印刷电路板上，使得第一和第二布线图案不相交。

公开(公告)号：US20130235542A1

公开(公告)日：2013-09-12

申请号：US13417103

申请日：2012-03-09

Applicant: Yunpeng SONG ,  Yongsheng LIU ,  Hongyu DENG

Inventor： Yunpeng SONG ,  Yongsheng LIU ,  Hongyu DENG

IPC: H01R9/00 ,  H05K1/02 ,  H01P1/04 ,  H05K1/11

CPC classification number: H01P5/08 ,  H01P1/047 ,  H01P3/003 ,  H01P3/08 ,  H05K1/0227 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/112 ,  H05K2201/09236

Abstract: In an example embodiment, an electronics package includes one or more insulating layers and an electrically conductive transmission line. The electrically conductive transmission line includes a signal trace disposed substantially parallel to the one or more insulating layers. The electrically conductive transmission line further includes one or more signal vias electrically coupled to the signal trace. The one or more signal vias are configured to pass through at least a portion of the one or more insulating layers. The electronics package further includes one or more electrically conductive ground planes substantially parallel to the one or more insulating layers. The ground planes include one or more signal via ground cuts. The one or more signal via ground cuts provide clearance between the one or more signal vias and the one or more ground planes.

Abstract translation: 在示例性实施例中，电子封装包括一个或多个绝缘层和导电传输线。 导电传输线包括基本上平行于一个或多个绝缘层设置的信号迹线。 导电传输线还包括电耦合到信号迹线的一个或多个信号通孔。 一个或多个信号通孔被配置成穿过一个或多个绝缘层的至少一部分。 电子封装还包括基本上平行于一个或多个绝缘层的一个或多个导电接地平面。 地平面包括一个或多个通过地面切割的信号。 通过接地切口的一个或多个信号在一个或多个信号通孔和一个或多个接地平面之间提供间隙。

公开(公告)号：US08528202B2

公开(公告)日：2013-09-10

申请号：US11513478

申请日：2005-02-17

Applicant: Tetsuo Yumoto

Inventor： Tetsuo Yumoto

IPC: H05K3/42

CPC classification number: G01R31/28 ,  H05K1/0284 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09236 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09854 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165 ,  Y10T29/49176

Abstract: A molding pin for a metal die is prevented from breaking, solder is surely deposited, and thus, a circuit pitch can be reduced to the limit. On the front plane of a circuit board, prescribed circuit patterns made of a conductive material are formed, and on the rear plane, prescribed circuit patterns are also formed. On the circuit board, a through hole is formed to carry electricity between the circuit patterns on both planes. The inner shape of the through hole is narrow in a direction between the adjacent circuit patterns and wide in a circuit extending direction.

Abstract translation: 防止金属模具的成型销断裂，确实沉积焊料，因此可以将电路间距减小到极限。 在电路板的正面上，形成由导电材料制成的规定的电路图案，在背面也形成规定的电路图形。 在电路板上，形成通孔，以在两个平面上的电路图案之间承载电力。 通孔的内部形状在相邻电路图案之间的方向上窄，并且在电路延伸方向上宽。

公开(公告)号：US08525611B2

公开(公告)日：2013-09-03

申请号：US13400965

申请日：2012-02-21

Applicant: Mohammad Tabatabai

Inventor： Mohammad Tabatabai

IPC: H01P3/08

CPC classification number: H01P3/026 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09318

Abstract: According to one exemplary embodiment, a circuit board for reducing dielectric loss, conductor loss, and insertion loss includes a pair of transmission lines. The pair of transmission lines has sufficient thickness to cause substantial broadside electromagnetic coupling between the pair of transmission lines, where the pair of transmission lines is sufficiently separated from a ground plane of the circuit board so as to cause negligible electromagnetic coupling to the ground plane relative to the substantial broadside electromagnetic coupling. The pair of transmission lines thereby reduce dielectric loss, conductor loss, and insertion loss for signals traversing through the transmission line pair. The pair of transmission lines can be separated from the ground plane by, for example, at least 50.0 mils.

Abstract translation: 根据一个示例性实施例，用于降低介质损耗，导体损耗和插入损耗的电路板包括一对传输线。 这对传输线具有足够的厚度，以在一对传输线之间产生实质的宽边电磁耦合，其中一对传输线与电路板的接地平面充分分离，从而使接地平面的电磁耦合可以忽略不计 到实质的宽边电磁耦合。 这对传输线因此减少了穿过传输线对的信号的介质损耗，导体损耗和插入损耗。 这对传输线可以通过例如至少50.0密耳从地平面分离。

公开(公告)号：US08487439B2

公开(公告)日：2013-07-16

申请号：US13237259

申请日：2011-09-20

Applicant: Makoto Tani ,  Takami Hirai ,  Shinsuke Yano ,  Tsutomu Nanataki

Inventor： Makoto Tani ,  Takami Hirai ,  Shinsuke Yano ,  Tsutomu Nanataki

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40

CPC classification number: H01L23/49822 ,  H01L23/15 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4629 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.

Abstract translation: 提供了可以降低与温度变化相关联地在半导体元件和板之间作用的热应力并且具有作为整个板（包括多层布线层）的高机械强度（刚性）的电路板。 具有与半导体元件和内层布线接近的热膨胀系数的陶瓷基材一体烧结，并且电路板被构造成使得与内层布线中的多层布线层相对应的细线导体结构具有预定的 宽度，内膜间隔和层间间隔。 因此，抑制了在与半导体元件接合的状态下板暴露于温度变化时半导体元件与基板之间的热应力，保持板的刚性，并且提高其对温度循环的可靠性。

公开(公告)号：US08481866B2

公开(公告)日：2013-07-09

申请号：US13187173

申请日：2011-07-20

Applicant: Jason Edward Chan ,  Jose Ricardo Paniagua

Inventor： Jason Edward Chan ,  Jose Ricardo Paniagua

IPC: H05K1/11

CPC classification number: H01R12/523 ,  H01R12/58 ,  H01R13/6461 ,  H01R13/6477 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09845 ,  H05K2203/0242

Abstract: An electrical signal connection, an electrical signaling system, and a method of connecting printed circuit boards. The electrical signal connection having a first conductive via and a second conductive via disposed in a first printed circuit board. A first conductive trace with a first end and a second end has the first end electrically coupled to the first conductive via at a first distance from the top surface of the first printed circuit board. The second end of the first conductive via is electrically coupled to the second printed circuit board. A second conductive trace with a first end and a second end has the first end being electrically coupled to the second conductive via at a second distance from the top surface of the first printed circuit board. The second end being is electrically coupled to the second printed circuit board.

Abstract translation: 电信号连接，电信号系统和连接印刷电路板的方法。 电信号连接具有设置在第一印刷电路板中的第一导电通孔和第二导电通孔。 具有第一端和第二端的第一导电迹线具有与第一印刷电路板的顶表面第一距离处电耦合到第一导电通孔的第一端。 第一导电通孔的第二端电耦合到第二印刷电路板。 具有第一端和第二端的第二导电迹线具有第一端部，其与第一印刷电路板的顶表面距离第二距离电耦合到第二导电通孔。 第二端电连接到第二印刷电路板。

公开(公告)号：US08476533B2

公开(公告)日：2013-07-02

申请号：US13238761

申请日：2011-09-21

Applicant: Fa-Ping Fan

Inventor： Fa-Ping Fan

IPC: H05K1/03

CPC classification number: H05K1/111 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09281 ,  Y02P70/611

Abstract: An exemplary printed circuit board includes a substrate, a differential transmission line, and at least two weld pad pairs. The differential transmission line and the at least two weld pad pairs are disposed on the substrate. The differential transmission line includes two parallel signal conductors disposed on the substrate. Each of the two signal conductors is electrically connected to an edge of one of the weld pads of a respective pair of the at least two weld pad pairs. Thereby, the two signal conductors of the differential transmission line can extend in the same distance anywhere, particularly in the position where the two signal conductors pass the two weld pad pairs. As a result, the coupling performance and the capability of the differential transmission line to resist electromagnetic interference are both enhanced.

Abstract translation: 示例性印刷电路板包括基板，差分传输线和至少两个焊盘对。 差分传输线和至少两个焊盘对设置在基板上。 差分传输线包括设置在基板上的两个并行信号导体。 两个信号导体中的每一个电连接到相应的一对至少两个焊盘对的焊接焊盘之一的边缘。 因此，差分传输线的两个信号导体可以在任何地方延伸相同的距离，特别是在两个信号导体通过两个焊盘对的位置。 结果，提高了耦合性能和差动传输线抵抗电磁干扰的能力。

公开(公告)号：US20130112468A1

公开(公告)日：2013-05-09

申请号：US13553414

申请日：2012-07-19

Applicant: Thomas S. COHEN ,  Marc B. Cartier, JR. ,  Mark W. Gailus

Inventor： Thomas S. COHEN ,  Marc B. Cartier, JR. ,  Mark W. Gailus

IPC: H05K1/11

CPC classification number: H01R13/646 ,  H01R13/514 ,  H01R13/6471 ,  H01R13/6587 ,  H01R23/688 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/115 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K7/1445 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.