公开(公告)号：US20060090335A1

公开(公告)日：2006-05-04

申请号：US11060497

申请日：2005-02-18

Applicant: Shih-Ping Hsu ,  Sao-Hsia Tang ,  Chao-Wen Shih

Inventor： Shih-Ping Hsu ,  Sao-Hsia Tang ,  Chao-Wen Shih

IPC: H01R43/00

CPC classification number: H05K3/243 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11902 ,  H01L2924/00014 ,  H05K3/28 ,  H05K3/3473 ,  H05K2201/0391 ,  H05K2201/09436 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/0574 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for fabricating connection terminals of a circuit board is proposed. The method involves providing a circuit board with connection pads thereon, forming an insulating layer with first openings over the circuit board to expose the connection pads, forming a conductive layer over the insulating layer, forming a first resist layer with second openings over the conductive layer to partially expose the conductive layer, electroplating a first metal connection layer on the exposed conductive layer, followed by forming a second resist layer with third openings over the first conductive layer to partially expose the first metal connection layer, and electroplating a second metal connection layer on the exposed first connection layer, and removing portions of the first and second resist layers and conductive layer covered by the first and second resist layers to form metal connection material of different heights and sizes on the connection pads.

Abstract translation: 提出了一种用于制造电路板的连接端子的方法。 该方法包括为电路板提供其上的连接焊盘，在电路板上形成具有第一开口的绝缘层，以暴露连接焊盘，在绝缘层上形成导电层，形成第一抗蚀剂层，第二开口穿过导电层 以部分地暴露所述导电层，在所述暴露的导电层上电镀第一金属连接层，随后在所述第一导电层上形成具有第三开口的第二抗蚀剂层以部分地暴露所述第一金属连接层，以及电镀第二金属连接层 在所述暴露的第一连接层上，以及去除所述第一和第二抗蚀剂层的部分和由所述第一和第二抗蚀剂层覆盖的导电层，以在所述连接焊盘上形成不同高度和尺寸的金属连接材料。

公开(公告)号：US20060081977A1

公开(公告)日：2006-04-20

申请号：US10549986

申请日：2004-10-15

Applicant: Norio Sakai ,  Jun Harada ,  Satoshi Ishino ,  Yoshihiko Nishizawa

Inventor： Norio Sakai ,  Jun Harada ,  Satoshi Ishino ,  Yoshihiko Nishizawa

IPC: H01L23/06

CPC classification number: H05K1/186 ,  H01L23/5385 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4605 ,  H05K2201/0154 ,  H05K2201/09436 ,  H05K2203/1581 ,  H01L2224/0401

Abstract: A ceramic multilayer substrate has a ceramic laminate including a plurality of ceramic layers laminated, having a first main surface, and including internal circuit elements disposed in the inside, a resin layer having a bonding surface in contact with the first main surface of the ceramic laminate and a mounting surface opposite to the bonding surface, external electrodes, each disposed on the mounting surface of the resin layer and electrically connected to at least one of the internal circuit elements of the ceramic laminate, and a ground electrode, a dummy electrode, or capacitor electrodes disposed at an interface between the first main surface of the ceramic laminate and the bonding surface of the resin layer or in the inside of the resin layer.

Abstract translation: 陶瓷多层基板具有包括多个陶瓷层的陶瓷层叠体，具有第一主表面，并且包括设置在内部的内部电路元件，具有与陶瓷层叠体的第一主表面接触的接合面的树脂层 和与接合面相反的安装面，外部电极，各自设置在树脂层的安装面上，与陶瓷层叠体的至少一个内部电路元件电连接，接地电极，虚拟电极或 设置在陶瓷层叠体的第一主面与树脂层的接合面或树脂层内侧的界面处的电容电极。

公开(公告)号：US20060060956A1

公开(公告)日：2006-03-23

申请号：US10948386

申请日：2004-09-22

Applicant: Ravindra Tanikella

Inventor： Ravindra Tanikella

IPC: H01L23/02

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

Abstract translation: 用于微电子封装的高度可靠的互连。 在一个实施例中，积层互连中的电介质层具有玻璃化转变温度的等级; 并且稍后施加的电介质层在低于较早施加的电介质层的玻璃化转变温度的温度下被层压。 在一个实施方案中，通过热固化工艺增加了积聚互连中早期施加的介电膜的玻璃化转变温度，以超过用于层压后来施加的电介质膜的温度。 在一个实施方案中，在层压聚酰亚胺材料的膜（例如，通过催化剂的密封剂的光化学或热降解）之后，用嵌入的催化剂形成聚酰亚胺材料以促进交联。 在一个实施例中，阻焊剂开口壁具有通过激光辅助接种产生的可湿性层，使得阻焊剂开口壁之间没有间隙，并且在阻焊剂开口中没有底部填充物。

公开(公告)号：US06995026B2

公开(公告)日：2006-02-07

申请号：US10775736

申请日：2004-02-10

Applicant: Stephen Moxham ,  William Stephenson

Inventor： Stephen Moxham ,  William Stephenson

IPC: G01R31/26 ,  H01L21/66

CPC classification number: H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method and apparatus for supporting a microelectronic substrate. The apparatus can include a microelectronic substrate and a support member carrying the microelectronic substrate. The apparatus can further include a first connection structure carried by the support member. The first connection structure can have a first bond site configured to receive a flowable conductive material, and can further have at least two first elongated members connected and extending outwardly from the first bond site. Each first elongated member can be configured to receive at least a portion of the flowable conductive material from the first bond site, with none of the first elongated members being electrically coupled to the microelectronic substrate. The assembly can further include a second connection structure that is electrically coupled to the microelectronic substrate and that can include second elongated members extending away from a second bond site. The number of second elongated members can be equal to the number of first elongated members.

Abstract translation: 一种用于支撑微电子衬底的方法和装置。 该装置可以包括微电子衬底和承载微电子衬底的支撑构件。 该装置还可以包括由支撑构件承载的第一连接结构。 第一连接结构可以具有构造成接收可流动的导电材料的第一接合位置，并且还可以具有连接并从第一接合位置向外延伸的至少两个第一细长构件。 每个第一细长构件可以被构造成从第一接合位置接收可流动的导电材料的至少一部分，而第一细长构件没有一个电耦合到微电子衬底。 组件还可以包括电耦合到微电子衬底的第二连接结构，并且可以包括远离第二接合位置延伸的第二细长构件。 第二细长构件的数量可以等于第一细长构件的数量。

公开(公告)号：US06961995B2

公开(公告)日：2005-11-08

申请号：US10251072

申请日：2002-09-19

Applicant: Lisa J. Jimarez ,  Miguel A. Jimarez ,  Voya R. Markovich ,  Cynthia S. Milkovich ,  Charles H. Perry ,  Brenda L. Peterson

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez ,  Voya R. Markovich ,  Cynthia S. Milkovich ,  Charles H. Perry ,  Brenda L. Peterson

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10 ,  B44C1/22 ,  C03C15/00 ,  H05K7/12 ,  C23E1/00

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/4605 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/061 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

公开(公告)号：US20050072597A1

公开(公告)日：2005-04-07

申请号：US10891921

申请日：2004-07-15

Applicant: Chun-Yu Lee ,  Shy-Ping Chou ,  Hui-Chang Chen

Inventor： Chun-Yu Lee ,  Shy-Ping Chou ,  Hui-Chang Chen

IPC: G02F1/13 ,  H05K1/11 ,  H05K3/22 ,  H05K3/32 ,  H05K3/36

CPC classification number: G02F1/13452 ,  H05K1/113 ,  H05K3/225 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09436 ,  H05K2201/09509

Abstract: A bonding pad structure of a display device. A first conductive layer is formed overlying a substrate, a protection layer is formed overlying the substrate and the first conductive layer, and a second conductive layer is formed overlying the protection layer. An opening structure penetrates the second conductive layer and the protection layer to expose the first conductive layer. A third conductive layer is formed overlying the second conductive layer to contact the sidewall and bottom of the opening structure. Thus, the third conductive layer is electrically connected to the second conductive layer to provide a first electrical-connection path, and the third conductive layer is electrically connected to the first conductive layer to provide a second electrical-connection path.

Abstract translation: 一种显示装置的焊盘结构。 第一导电层形成在衬底上，覆盖衬底和第一导电层形成保护层，并且形成覆盖保护层的第二导电层。 开口结构穿透第二导电层和保护层以暴露第一导电层。 形成第三导电层，覆盖第二导电层以接触开口结构的侧壁和底部。 因此，第三导电层电连接到第二导电层以提供第一电连接路径，并且第三导电层电连接到第一导电层以提供第二电连接路径。

公开(公告)号：US20050054187A1

公开(公告)日：2005-03-10

申请号：US10933350

申请日：2004-09-03

Applicant: Yi-Chuan Ding ,  Shun-Fu Ko

Inventor： Yi-Chuan Ding ,  Shun-Fu Ko

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/06 ,  H05K3/34 ,  H05K3/42 ,  H01L21/44 ,  H01L21/50 ,  H01L23/52

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/112 ,  H05K3/061 ,  H05K3/062 ,  H05K3/3484 ,  H05K3/421 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2203/054 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for forming ball pads of a BGA substrate is disclosed. A substrate is provided with a plurality of pad terminals on its surface. A solder mask is formed on the surface and has a plurality of openings to expose the pad terminals. A metal layer for redefining ball pads is formed on the solder mask. An etching mask is formed on the metal layer, the etching mask has a plurality of covering portions which are aligned with the pad terminals and larger than the openings of the solder mask. The metal layer is etched to form a plurality of redefined ball pads under the etching mask. The redefined ball pads cover the pad terminals of the substrate and extend around the openings of the solder mask so that solder balls can be jointed with the redefined ball pads to avoid contacting the solder mask and the pad terminals by redefinition of bonding area of solder balls.

Abstract translation: 公开了一种用于形成BGA衬底的球垫的方法。 基板在其表面上设置有多个焊盘端子。 在该表面上形成焊接掩模，并且具有多个开口以露出焊盘端子。 在焊接掩模上形成用于重新定义球垫的金属层。 在金属层上形成蚀刻掩模，蚀刻掩模具有与焊盘端子对准的多个覆盖部分，并且大于焊料掩模的开口。 蚀刻金属层以在蚀刻掩模下形成多个重新定义的球垫。 重新定义的球垫覆盖基板的焊盘端子并围绕焊接掩模的开口延伸，使得焊球可以与重新定义的焊盘接合，以避免通过重新定义焊球的焊接区域而接触焊接掩模和焊盘端子 。

公开(公告)号：US20050017058A1

公开(公告)日：2005-01-27

申请号：US10710561

申请日：2004-07-21

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: B23K1/00 ,  B23K1/19 ,  B23K1/20 ,  H01L21/48 ,  H05K3/24 ,  H05K3/28 ,  B23K31/02

CPC classification number: H01L21/4857 ,  B23K1/0018 ,  B23K1/19 ,  B23K1/20 ,  B23K2101/42 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/054 ,  H05K2203/0542

Abstract: The present invention provides a method of fabricating a circuit substrate. First, a substrate having first pads and second pads is provided, wherein the first pads and second pads are arranged respectively on a first surface and a second surface of the substrate. The first pads are electrically connected to the second pads. Next, a conductive seed layer is formed on the second surface of the circuit substrate. Thereafter, a first conductive layer and a second conductive layer are electroplated respectively over the first pads and the second pads. Afterwards, the conductive seed layer is patterned.

Abstract translation: 本发明提供一种制造电路基板的方法。 首先，提供具有第一焊盘和第二焊盘的衬底，其中第一焊盘和第二焊盘分别布置在衬底的第一表面和第二表面上。 第一焊盘电连接到第二焊盘。 接下来，在电路基板的第二表面上形成导电种子层。 此后，分别在第一焊盘和第二焊盘上电镀第一导电层和第二导电层。 之后，对导电种子层进行图案化。

公开(公告)号：US06841225B2

公开(公告)日：2005-01-11

申请号：US10435183

申请日：2003-05-09

Applicant: Frank J. Bottari

Inventor： Frank J. Bottari

IPC: G06F3/033 ,  G06F3/045 ,  H05K3/20 ,  H05K3/28 ,  G09G5/00

CPC classification number: G06F3/045 ,  H05K3/207 ,  H05K3/28 ,  H05K2201/0284 ,  H05K2201/09436 ,  H05K2203/0531 ,  Y10S428/914 ,  Y10T29/49117 ,  Y10T428/24777 ,  Y10T428/24917

Abstract: A method of applying an edge electrode pattern to a touch screen panel including printing an edge electrode pattern on decal paper; applying a cover coat over the electrode pattern; removing the decal paper; and transferring the edge electrode pattern to a touch screen panel. A decal to be used in accordance with this method.

Abstract translation: 一种将边缘电极图案应用于触摸屏面板的方法，包括在贴纸上印刷边缘电极图案; 在电极图案上涂覆覆盖层; 去除贴纸; 并将边缘电极图案转移到触摸屏面板。 按照这种方法使用的贴花。

公开(公告)号：US20040212087A1

公开(公告)日：2004-10-28

申请号：US10709096

申请日：2004-04-13

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kei MURAYAMA ,  Masahiro SUNOHARA

IPC: H01L023/48

CPC classification number: H01L23/49827 ,  H01L23/562 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/81206 ,  H01L2224/81801 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H05K1/113 ,  H05K3/328 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10674 ,  H05K2203/0285 ,  H01L2924/00

Abstract: In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support the connection pad upon the ultrasonic flip-chip packaging is filled is arranged in the insulating film under the connection pad.

Abstract translation: 在本发明的布线基板中，电子部件的凸块通过超声波倒装芯片封装被接合到设置在绝缘膜上的布线图案的连接焊盘，通孔，通孔作为 在超声波倒装芯片封装被填充的支撑件支撑连接垫被布置在连接垫下面的绝缘膜中。